2015-05-19 12:18:04 +01:00
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/*
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2018-10-17 15:29:34 +01:00
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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2015-05-19 12:18:04 +01:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2015-05-19 12:18:04 +01:00
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#include <cortex_a53.h>
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2017-07-14 10:46:32 +01:00
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#include <cortex_a57.h>
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2016-04-26 19:38:38 +01:00
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#include <platform_def.h>
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2015-05-19 12:18:04 +01:00
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#include <tegra_def.h>
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2017-04-24 12:35:51 +01:00
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#include <tegra_platform.h>
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2015-05-19 12:18:04 +01:00
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2015-09-22 09:03:56 +01:00
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#define MIDR_PN_CORTEX_A57 0xD07
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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2017-06-14 07:02:23 +01:00
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#define ACTLR_EL3_L2ACTLR_BIT (U(1) << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (U(1) << 5)
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#define ACTLR_EL3_L2CTLR_BIT (U(1) << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (U(1) << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (U(1) << 0)
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#define ACTLR_EL3_ENABLE_ALL_MASK (ACTLR_EL3_L2ACTLR_BIT | \
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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2015-09-22 09:03:56 +01:00
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#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
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2017-06-14 07:02:23 +01:00
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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2015-09-22 09:03:56 +01:00
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2015-05-19 12:18:04 +01:00
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/* Global functions */
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2015-08-07 05:33:00 +01:00
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_get_my_entrypoint
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2015-05-19 12:18:04 +01:00
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.globl plat_secondary_cold_boot_setup
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.globl platform_mem_init
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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2018-10-17 15:29:34 +01:00
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.globl plat_crash_console_flush
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2015-05-19 12:18:04 +01:00
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.globl tegra_secure_entrypoint
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.globl plat_reset_handler
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/* Global variables */
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2015-08-07 05:33:00 +01:00
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.globl tegra_sec_entry_point
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2015-05-19 12:18:04 +01:00
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.globl ns_image_entrypoint
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.globl tegra_bl31_phys_base
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2015-10-29 05:07:28 +00:00
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.globl tegra_console_base
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2015-05-19 12:18:04 +01:00
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/* ---------------------
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* Common CPU init code
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* ---------------------
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*/
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.macro cpu_init_common
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2015-09-22 09:03:56 +01:00
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/* ------------------------------------------------
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2016-05-12 21:43:33 +01:00
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* We enable procesor retention, L2/CPUECTLR NS
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* access and ECC/Parity protection for A57 CPUs
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2015-09-22 09:03:56 +01:00
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* ------------------------------------------------
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*/
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mrs x0, midr_el1
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mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT)
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and x0, x0, x1
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lsr x0, x0, #MIDR_PN_SHIFT
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cmp x0, #MIDR_PN_CORTEX_A57
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b.ne 1f
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2015-08-21 11:26:02 +01:00
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/* ---------------------------
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* Enable processor retention
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* ---------------------------
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2016-05-12 21:43:33 +01:00
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*/
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2017-06-05 22:54:46 +01:00
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mrs x0, CORTEX_A57_L2ECTLR_EL1
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mov x1, #RETENTION_ENTRY_TICKS_512
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bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK
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2015-08-21 11:26:02 +01:00
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orr x0, x0, x1
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2017-06-05 22:54:46 +01:00
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msr CORTEX_A57_L2ECTLR_EL1, x0
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2015-08-21 11:26:02 +01:00
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isb
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2017-06-05 22:54:46 +01:00
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mrs x0, CORTEX_A57_ECTLR_EL1
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mov x1, #RETENTION_ENTRY_TICKS_512
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bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK
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2015-08-21 11:26:02 +01:00
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orr x0, x0, x1
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2017-06-05 22:54:46 +01:00
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msr CORTEX_A57_ECTLR_EL1, x0
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2015-08-21 11:26:02 +01:00
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isb
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2015-05-19 12:18:04 +01:00
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/* -------------------------------------------------------
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* Enable L2 and CPU ECTLR RW access from non-secure world
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* -------------------------------------------------------
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2016-05-12 21:43:33 +01:00
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*/
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2017-06-14 07:02:23 +01:00
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mrs x0, actlr_el3
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mov x1, #ACTLR_EL3_ENABLE_ALL_MASK
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bic x0, x0, x1
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mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS
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orr x0, x0, x1
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2015-05-19 12:18:04 +01:00
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msr actlr_el3, x0
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2017-06-14 07:02:23 +01:00
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mrs x0, actlr_el2
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mov x1, #ACTLR_EL3_ENABLE_ALL_MASK
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bic x0, x0, x1
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mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS
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orr x0, x0, x1
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2015-05-19 12:18:04 +01:00
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msr actlr_el2, x0
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isb
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/* --------------------------------
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* Enable the cycle count register
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* --------------------------------
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*/
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2015-09-22 09:03:56 +01:00
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1: mrs x0, pmcr_el0
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2015-05-19 12:18:04 +01:00
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ubfx x0, x0, #11, #5 // read PMCR.N field
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mov x1, #1
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lsl x0, x1, x0
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sub x0, x0, #1 // mask of event counters
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orr x0, x0, #0x80000000 // disable overflow intrs
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msr pmintenclr_el1, x0
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msr pmuserenr_el0, x1 // enable user mode access
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/* ----------------------------------------------------------------
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* Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count
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* register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ
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* registers from EL0.
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* ----------------------------------------------------------------
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*/
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mrs x0, cntkctl_el1
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orr x0, x0, #EL0VCTEN_BIT
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msr cntkctl_el1, x0
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.endm
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/* -----------------------------------------------------
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2015-08-07 05:33:00 +01:00
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* unsigned int plat_is_my_cpu_primary(void);
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2015-05-19 12:18:04 +01:00
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*
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* This function checks if this is the Primary CPU
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* -----------------------------------------------------
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*/
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2015-08-07 05:33:00 +01:00
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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2015-05-19 12:18:04 +01:00
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #TEGRA_PRIMARY_CPU
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cset x0, eq
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ret
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2015-08-07 05:33:00 +01:00
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endfunc plat_is_my_cpu_primary
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2015-05-19 12:18:04 +01:00
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2017-08-24 00:02:06 +01:00
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/* ----------------------------------------------------------
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2015-08-07 05:33:00 +01:00
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* unsigned int plat_my_core_pos(void);
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*
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2017-08-24 00:02:06 +01:00
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* result: CorePos = CoreId + (ClusterId * cpus per cluster)
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* ----------------------------------------------------------
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2015-08-07 05:33:00 +01:00
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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2017-08-24 00:02:06 +01:00
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lsr x0, x0, #MPIDR_AFFINITY_BITS
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mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER
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mul x0, x0, x2
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add x0, x1, x0
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2015-08-07 05:33:00 +01:00
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ret
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between
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* a cold and warm boot. If the tegra_sec_entry_point for
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* this CPU is present, then it's a warm boot.
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2015-05-19 12:18:04 +01:00
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*
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* -----------------------------------------------------
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*/
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2015-08-07 05:33:00 +01:00
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func plat_get_my_entrypoint
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adr x1, tegra_sec_entry_point
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ldr x0, [x1]
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2015-05-19 12:18:04 +01:00
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ret
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2015-08-07 05:33:00 +01:00
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endfunc plat_get_my_entrypoint
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2015-05-19 12:18:04 +01:00
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2015-09-22 09:15:07 +01:00
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/* -----------------------------------------------------
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* int platform_get_core_pos(int mpidr);
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*
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2017-08-24 00:02:06 +01:00
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* result: CorePos = (ClusterId * cpus per cluster) +
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* CoreId
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2015-09-22 09:15:07 +01:00
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* -----------------------------------------------------
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*/
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func platform_get_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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2017-08-24 00:02:06 +01:00
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lsr x0, x0, #MPIDR_AFFINITY_BITS
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mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER
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mul x0, x0, x2
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add x0, x1, x0
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2015-09-22 09:15:07 +01:00
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ret
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endfunc platform_get_core_pos
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2015-05-19 12:18:04 +01:00
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset. Right
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* now this is a stub function.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mov x0, #0
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ret
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endfunc plat_secondary_cold_boot_setup
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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mov x0, #0
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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2015-11-26 14:52:15 +00:00
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* Clobber list : x0 - x4
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2015-05-19 12:18:04 +01:00
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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2017-04-04 21:40:12 +01:00
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mov x0, #0
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adr x1, tegra_console_base
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ldr x1, [x1]
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cbz x1, 1f
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mov w0, #1
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1: ret
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2015-05-19 12:18:04 +01:00
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(void)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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2015-10-29 05:07:28 +00:00
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adr x1, tegra_console_base
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ldr x1, [x1]
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2015-05-19 12:18:04 +01:00
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b console_core_putc
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endfunc plat_crash_console_putc
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2018-10-17 15:29:34 +01:00
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/* ---------------------------------------------
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* int plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : return -1 on error else return 0.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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adr x0, tegra_console_base
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ldr x0, [x0]
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b console_core_flush
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endfunc plat_crash_console_flush
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2015-05-19 12:18:04 +01:00
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/* ---------------------------------------------------
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* Function to handle a platform reset and store
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* input parameters passed by BL2.
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* ---------------------------------------------------
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*/
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func plat_reset_handler
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2016-03-24 22:34:24 +00:00
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/* ----------------------------------------------------
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* Verify if we are running from BL31_BASE address
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* ----------------------------------------------------
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*/
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adr x18, bl31_entrypoint
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mov x17, #BL31_BASE
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cmp x18, x17
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b.eq 1f
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/* ----------------------------------------------------
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* Copy the entire BL31 code to BL31_BASE if we are not
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* running from it already
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* ----------------------------------------------------
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*/
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mov x0, x17
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mov x1, x18
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mov x2, #BL31_SIZE
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_loop16:
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cmp x2, #16
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2017-03-20 10:38:29 +00:00
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b.lo _loop1
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2016-03-24 22:34:24 +00:00
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ldp x3, x4, [x1], #16
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stp x3, x4, [x0], #16
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sub x2, x2, #16
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b _loop16
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/* copy byte per byte */
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_loop1:
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cbz x2, _end
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ldrb w3, [x1], #1
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne _loop1
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/* ----------------------------------------------------
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* Jump to BL31_BASE and start execution again
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* ----------------------------------------------------
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*/
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_end: mov x0, x20
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mov x1, x21
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br x17
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1:
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2015-05-19 12:18:04 +01:00
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/* -----------------------------------
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* derive and save the phys_base addr
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* -----------------------------------
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*/
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adr x17, tegra_bl31_phys_base
|
|
|
|
ldr x18, [x17]
|
|
|
|
cbnz x18, 1f
|
|
|
|
adr x18, bl31_entrypoint
|
|
|
|
str x18, [x17]
|
|
|
|
|
|
|
|
1: cpu_init_common
|
|
|
|
|
|
|
|
ret
|
|
|
|
endfunc plat_reset_handler
|
|
|
|
|
|
|
|
/* ----------------------------------------
|
|
|
|
* Secure entrypoint function for CPU boot
|
|
|
|
* ----------------------------------------
|
|
|
|
*/
|
Add new alignment parameter to func assembler macro
Assembler programmers are used to being able to define functions with a
specific aligment with a pattern like this:
.align X
myfunction:
However, this pattern is subtly broken when instead of a direct label
like 'myfunction:', you use the 'func myfunction' macro that's standard
in Trusted Firmware. Since the func macro declares a new section for the
function, the .align directive written above it actually applies to the
*previous* section in the assembly file, and the function it was
supposed to apply to is linked with default alignment.
An extreme case can be seen in Rockchip's plat_helpers.S which contains
this code:
[...]
endfunc plat_crash_console_putc
.align 16
func platform_cpu_warmboot
[...]
This assembles into the following plat_helpers.o:
Sections:
Idx Name Size [...] Algn
9 .text.plat_crash_console_putc 00010000 [...] 2**16
10 .text.platform_cpu_warmboot 00000080 [...] 2**3
As can be seen, the *previous* function actually got the alignment
constraint, and it is also 64KB big even though it contains only two
instructions, because the .align directive at the end of its section
forces the assembler to insert a giant sled of NOPs. The function we
actually wanted to align has the default constraint. This code only
works at all because the linker just happens to put the two functions
right behind each other when linking the final image, and since the end
of plat_crash_console_putc is aligned the start of platform_cpu_warmboot
will also be. But it still wastes almost 64KB of image space
unnecessarily, and it will break under certain circumstances (e.g. if
the plat_crash_console_putc function becomes unused and its section gets
garbage-collected out).
There's no real way to fix this with the existing func macro. Code like
func myfunc
.align X
happens to do the right thing, but is still not really correct code
(because the function label is inserted before the .align directive, so
the assembler is technically allowed to insert padding at the beginning
of the function which would then get executed as instructions if the
function was called). Therefore, this patch adds a new parameter with a
default value to the func macro that allows overriding its alignment.
Also fix up all existing instances of this dangerous antipattern.
Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10
Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-08-01 23:16:36 +01:00
|
|
|
func tegra_secure_entrypoint _align=6
|
2015-05-19 12:18:04 +01:00
|
|
|
|
|
|
|
#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT
|
|
|
|
|
2017-04-24 12:35:51 +01:00
|
|
|
/* --------------------------------------------------------
|
|
|
|
* Skip the invalidate BTB workaround for Tegra210B01 SKUs.
|
|
|
|
* --------------------------------------------------------
|
|
|
|
*/
|
|
|
|
mov x0, #TEGRA_MISC_BASE
|
|
|
|
add x0, x0, #HARDWARE_REVISION_OFFSET
|
|
|
|
ldr w1, [x0]
|
|
|
|
lsr w1, w1, #CHIP_ID_SHIFT
|
|
|
|
and w1, w1, #CHIP_ID_MASK
|
|
|
|
cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */
|
|
|
|
b.ne 2f
|
|
|
|
ldr w1, [x0]
|
|
|
|
lsr w1, w1, #MAJOR_VERSION_SHIFT
|
|
|
|
and w1, w1, #MAJOR_VERSION_MASK
|
|
|
|
cmp w1, #0x02 /* T210 B01? */
|
|
|
|
b.eq 2f
|
|
|
|
|
2015-05-19 12:18:04 +01:00
|
|
|
/* -------------------------------------------------------
|
|
|
|
* Invalidate BTB along with I$ to remove any stale
|
|
|
|
* entries from the branch predictor array.
|
|
|
|
* -------------------------------------------------------
|
|
|
|
*/
|
2017-08-10 14:46:26 +01:00
|
|
|
mrs x0, CORTEX_A57_CPUACTLR_EL1
|
2015-05-19 12:18:04 +01:00
|
|
|
orr x0, x0, #1
|
2017-08-10 14:46:26 +01:00
|
|
|
msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
|
2015-05-19 12:18:04 +01:00
|
|
|
dsb sy
|
|
|
|
isb
|
|
|
|
ic iallu /* actual invalidate */
|
|
|
|
dsb sy
|
|
|
|
isb
|
|
|
|
|
2017-08-10 14:46:26 +01:00
|
|
|
mrs x0, CORTEX_A57_CPUACTLR_EL1
|
2015-05-19 12:18:04 +01:00
|
|
|
bic x0, x0, #1
|
2017-08-10 14:46:26 +01:00
|
|
|
msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
|
2015-05-19 12:18:04 +01:00
|
|
|
dsb sy
|
|
|
|
isb
|
|
|
|
|
|
|
|
.rept 7
|
|
|
|
nop /* wait */
|
|
|
|
.endr
|
|
|
|
|
|
|
|
/* -----------------------------------------------
|
|
|
|
* Extract OSLK bit and check if it is '1'. This
|
|
|
|
* bit remains '0' for A53 on warm-resets. If '1',
|
|
|
|
* turn off regional clock gating and request warm
|
|
|
|
* reset.
|
|
|
|
* -----------------------------------------------
|
|
|
|
*/
|
|
|
|
mrs x0, oslsr_el1
|
|
|
|
and x0, x0, #2
|
|
|
|
mrs x1, mpidr_el1
|
|
|
|
bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */
|
|
|
|
b.eq restore_oslock
|
|
|
|
mov x0, xzr
|
|
|
|
msr oslar_el1, x0 /* os lock stays 0 across warm reset */
|
|
|
|
mov x3, #3
|
|
|
|
movz x4, #0x8000, lsl #48
|
2017-08-10 14:46:26 +01:00
|
|
|
msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */
|
2015-05-19 12:18:04 +01:00
|
|
|
isb
|
|
|
|
msr rmr_el3, x3 /* request warm reset */
|
|
|
|
isb
|
|
|
|
dsb sy
|
|
|
|
1: wfi
|
|
|
|
b 1b
|
|
|
|
|
|
|
|
/* --------------------------------------------------
|
|
|
|
* These nops are here so that speculative execution
|
|
|
|
* won't harm us before we are done with warm reset.
|
|
|
|
* --------------------------------------------------
|
|
|
|
*/
|
|
|
|
.rept 65
|
|
|
|
nop
|
|
|
|
.endr
|
2017-04-24 12:35:51 +01:00
|
|
|
2:
|
2015-05-19 12:18:04 +01:00
|
|
|
/* --------------------------------------------------
|
|
|
|
* Do not insert instructions here
|
|
|
|
* --------------------------------------------------
|
|
|
|
*/
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* --------------------------------------------------
|
|
|
|
* Restore OS Lock bit
|
|
|
|
* --------------------------------------------------
|
|
|
|
*/
|
|
|
|
restore_oslock:
|
|
|
|
mov x0, #1
|
|
|
|
msr oslar_el1, x0
|
|
|
|
|
|
|
|
/* --------------------------------------------------
|
|
|
|
* Get secure world's entry point and jump to it
|
|
|
|
* --------------------------------------------------
|
|
|
|
*/
|
2015-08-07 05:33:00 +01:00
|
|
|
bl plat_get_my_entrypoint
|
2015-05-19 12:18:04 +01:00
|
|
|
br x0
|
|
|
|
endfunc tegra_secure_entrypoint
|
|
|
|
|
|
|
|
.data
|
|
|
|
.align 3
|
|
|
|
|
|
|
|
/* --------------------------------------------------
|
2015-08-07 05:33:00 +01:00
|
|
|
* CPU Secure entry point - resume from suspend
|
2015-05-19 12:18:04 +01:00
|
|
|
* --------------------------------------------------
|
|
|
|
*/
|
2015-08-07 05:33:00 +01:00
|
|
|
tegra_sec_entry_point:
|
2015-05-19 12:18:04 +01:00
|
|
|
.quad 0
|
|
|
|
|
|
|
|
/* --------------------------------------------------
|
|
|
|
* NS world's cold boot entry point
|
|
|
|
* --------------------------------------------------
|
|
|
|
*/
|
|
|
|
ns_image_entrypoint:
|
|
|
|
.quad 0
|
|
|
|
|
|
|
|
/* --------------------------------------------------
|
|
|
|
* BL31's physical base address
|
|
|
|
* --------------------------------------------------
|
|
|
|
*/
|
|
|
|
tegra_bl31_phys_base:
|
|
|
|
.quad 0
|
2015-10-29 05:07:28 +00:00
|
|
|
|
|
|
|
/* --------------------------------------------------
|
|
|
|
* UART controller base for console init
|
|
|
|
* --------------------------------------------------
|
|
|
|
*/
|
|
|
|
tegra_console_base:
|
|
|
|
.quad 0
|