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arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_clock.h

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zynqmp: pm: Add clock control EEMI API and ioctl functions These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:25 +00:00
/*
zynqmp: pm: Rename FPD WDT clock ID This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT. Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I4d00a59b1dc54920115a2da55e8a06347fe2231c
2019-01-09 12:08:12 +00:00
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
zynqmp: pm: Add clock control EEMI API and ioctl functions These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:25 +00:00
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* ZynqMP system level PM-API functions for clock control.
*/
Standardise header guards across codebase All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-08 10:20:19 +00:00
#ifndef PM_API_CLOCK_H
#define PM_API_CLOCK_H
zynqmp: pm: Add clock control EEMI API and ioctl functions These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:25 +00:00
Sanitise includes across codebase Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-12-14 00:18:21 +00:00
#include <lib/utils_def.h>
zynqmp: pm: Add clock control EEMI API and ioctl functions These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:25 +00:00
#include "pm_common.h"
zynqmp: pm: Minor corrections for MISRA compliance Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-02-08 00:25:41 +00:00
#define CLK_NAME_LEN U(15)
#define MAX_PARENTS U(100)
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
#define CLK_NA_PARENT -1
#define CLK_DUMMY_PARENT -2
/* Flags for parent id */
zynqmp: pm: Minor corrections for MISRA compliance Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-02-08 00:25:41 +00:00
#define PARENT_CLK_SELF U(0)
#define PARENT_CLK_NODE1 U(1)
#define PARENT_CLK_NODE2 U(2)
#define PARENT_CLK_NODE3 U(3)
#define PARENT_CLK_NODE4 U(4)
#define PARENT_CLK_EXTERNAL U(5)
#define PARENT_CLK_MIO0_MIO77 U(6)
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
/* unused */
#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
/* parents need enable during gate/ungate, set rate and re-parent */
#define CLK_OPS_PARENT_ENABLE BIT(12)
#define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
#define CLK_DIVIDER_HIWORD_MASK BIT(3)
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
zynqmp: pm: clock: Move custom flags to typeflags Linux expects custom flags in type flags. So move custom flags to type flags instead of providing them to clock core flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78
2019-03-15 08:49:26 +00:00
#define CLK_FRAC BIT(8)
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
#define END_OF_CLK "END_OF_CLK"
zynqmp: pm: Minor corrections for MISRA compliance Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-02-08 00:25:41 +00:00
//CLock Ids
zynqmp: pm: Get PLL fractional data using PLL get parameter EEMI API Fractional data should be get using PLL get parameter EEMI API. This stands for system-level communication (APU to PMU). Since linux already uses a specific IOCTL function to do this and we need to keep it that way, the pll clock ID given by linux has to be mapped to the pll node ID that is communicated at the system-level (argument of PLL get parameter API). With this modification the function pm_api_clk_get_pll_frac_data is removed from pm_api_clock.c/h because it became unused. The clock enum is defined as 'enum clock_id'. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-02 20:40:17 +00:00
enum clock_id {
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
CLK_IOPLL,
CLK_RPLL,
CLK_APLL,
CLK_DPLL,
CLK_VPLL,
CLK_IOPLL_TO_FPD,
CLK_RPLL_TO_FPD,
CLK_APLL_TO_LPD,
CLK_DPLL_TO_LPD,
CLK_VPLL_TO_LPD,
CLK_ACPU,
CLK_ACPU_HALF,
CLK_DBG_FPD,
CLK_DBG_LPD,
CLK_DBG_TRACE,
CLK_DBG_TSTMP,
CLK_DP_VIDEO_REF,
CLK_DP_AUDIO_REF,
CLK_DP_STC_REF,
CLK_GDMA_REF,
CLK_DPDMA_REF,
CLK_DDR_REF,
CLK_SATA_REF,
CLK_PCIE_REF,
CLK_GPU_REF,
CLK_GPU_PP0_REF,
CLK_GPU_PP1_REF,
CLK_TOPSW_MAIN,
CLK_TOPSW_LSBUS,
CLK_GTGREF0_REF,
CLK_LPD_SWITCH,
CLK_LPD_LSBUS,
CLK_USB0_BUS_REF,
CLK_USB1_BUS_REF,
CLK_USB3_DUAL_REF,
CLK_USB0,
CLK_USB1,
CLK_CPU_R5,
CLK_CPU_R5_CORE,
CLK_CSU_SPB,
CLK_CSU_PLL,
CLK_PCAP,
CLK_IOU_SWITCH,
CLK_GEM_TSU_REF,
CLK_GEM_TSU,
CLK_GEM0_TX,
CLK_GEM1_TX,
CLK_GEM2_TX,
CLK_GEM3_TX,
zynqmp: pm: Fix clock models and IDs of GEM-related clocks GEM-related clock models were incorrect and are fixed as follows (documented below for GEM0, but the same holds for any GEM ID): - CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this clock is newly introduced in this patch. - CLK_GEM0_REF models the clock mux that selects the reference clock for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL. Note that the routing of external clock to the mux is not modelled and is assumed to be configured by the FSBL if required, and not changeable at runtime. The ID of this clock is introduced in this patch. - CLK_GEM0_TX models clock with only a gate that is controlled via bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID value of CLK_GEM0_REF. This is done in order to fix the clock models and incorrect binding without requiring to change device-tree (binding of clock IDs to GEM interface). - CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced from external RGMII PHY (via MIO or EMIO). We do not model the whole clock path to the Rx gate, since this is configured by the FSBL and never changed at runtime (and there is no mechanism to change the path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX were swapped in device tree, so by fixing the IDs this way there is no need for device tree fix. Rates of the external RX/TX clocks can be specified in device tree if needed. Right now, that's not necessary because Tx clock is sourced from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas the Rx clock is sourced from external reference and the driver never attempts to get/get clock rate (only to enable it). If this changes in future, ATF clock model doesn't need to be changed. Instead, the clock rates for gem0_tx_ext and gem0_rx_ext have to be specified in device tree. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <will.wong@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79
2018-09-17 13:25:16 +01:00
CLK_GEM0_RX,
CLK_GEM1_RX,
CLK_GEM2_RX,
CLK_GEM3_RX,
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
CLK_QSPI_REF,
CLK_SDIO0_REF,
CLK_SDIO1_REF,
CLK_UART0_REF,
CLK_UART1_REF,
CLK_SPI0_REF,
CLK_SPI1_REF,
CLK_NAND_REF,
CLK_I2C0_REF,
CLK_I2C1_REF,
CLK_CAN0_REF,
CLK_CAN1_REF,
CLK_CAN0,
CLK_CAN1,
CLK_DLL_REF,
CLK_ADMA_REF,
CLK_TIMESTAMP_REF,
CLK_AMS_REF,
CLK_PL0_REF,
CLK_PL1_REF,
CLK_PL2_REF,
CLK_PL3_REF,
zynqmp: pm: Rename FPD WDT clock ID This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT. Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I4d00a59b1dc54920115a2da55e8a06347fe2231c
2019-01-09 12:08:12 +00:00
CLK_FPD_WDT,
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
CLK_IOPLL_INT,
CLK_IOPLL_PRE_SRC,
CLK_IOPLL_HALF,
CLK_IOPLL_INT_MUX,
CLK_IOPLL_POST_SRC,
CLK_RPLL_INT,
CLK_RPLL_PRE_SRC,
CLK_RPLL_HALF,
CLK_RPLL_INT_MUX,
CLK_RPLL_POST_SRC,
CLK_APLL_INT,
CLK_APLL_PRE_SRC,
CLK_APLL_HALF,
CLK_APLL_INT_MUX,
CLK_APLL_POST_SRC,
CLK_DPLL_INT,
CLK_DPLL_PRE_SRC,
CLK_DPLL_HALF,
CLK_DPLL_INT_MUX,
CLK_DPLL_POST_SRC,
CLK_VPLL_INT,
CLK_VPLL_PRE_SRC,
CLK_VPLL_HALF,
CLK_VPLL_INT_MUX,
CLK_VPLL_POST_SRC,
CLK_CAN0_MIO,
CLK_CAN1_MIO,
zynqmp: pm: Fix model of ACPU clocks In the existing model for ACPU clock the mux, divider, and gate were represented as one clock and ACPU_HALF was modelled as child of ACPU clock. This is not correct. ACPU clock model contains only mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF clocks which have only gates. The models of ACPU and ACPU_HALF clocks are fixed and ACPU_FULL clock is added. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-02 21:45:53 +00:00
CLK_ACPU_FULL,
zynqmp: pm: Fix clock models and IDs of GEM-related clocks GEM-related clock models were incorrect and are fixed as follows (documented below for GEM0, but the same holds for any GEM ID): - CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this clock is newly introduced in this patch. - CLK_GEM0_REF models the clock mux that selects the reference clock for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL. Note that the routing of external clock to the mux is not modelled and is assumed to be configured by the FSBL if required, and not changeable at runtime. The ID of this clock is introduced in this patch. - CLK_GEM0_TX models clock with only a gate that is controlled via bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID value of CLK_GEM0_REF. This is done in order to fix the clock models and incorrect binding without requiring to change device-tree (binding of clock IDs to GEM interface). - CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced from external RGMII PHY (via MIO or EMIO). We do not model the whole clock path to the Rx gate, since this is configured by the FSBL and never changed at runtime (and there is no mechanism to change the path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX were swapped in device tree, so by fixing the IDs this way there is no need for device tree fix. Rates of the external RX/TX clocks can be specified in device tree if needed. Right now, that's not necessary because Tx clock is sourced from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas the Rx clock is sourced from external reference and the driver never attempts to get/get clock rate (only to enable it). If this changes in future, ATF clock model doesn't need to be changed. Instead, the clock rates for gem0_tx_ext and gem0_rx_ext have to be specified in device tree. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <will.wong@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79
2018-09-17 13:25:16 +01:00
CLK_GEM0_REF,
CLK_GEM1_REF,
CLK_GEM2_REF,
CLK_GEM3_REF,
CLK_GEM0_REF_UNGATED,
CLK_GEM1_REF_UNGATED,
CLK_GEM2_REF_UNGATED,
CLK_GEM3_REF_UNGATED,
zynqmp: pm: Add LPD WDT clock to the pm_clock structure This patch adds LPD WDT clock node to the pm_clock clocks structure list so that LPD WDT can be used from Linux. Also this patch removes the CLK_LPD_LSBUS from invalid clock list to allow the registration of this clock to CCF framework as it is the parent of LPD WDT. Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403
2019-01-09 12:08:13 +00:00
CLK_LPD_WDT,
zynqmp: pm: Minor corrections for MISRA compliance Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-02-08 00:25:41 +00:00
END_OF_OUTPUT_CLKS,
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
};
zynqmp: pm: Minor corrections for MISRA compliance Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-02-08 00:25:41 +00:00
#define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS)
//External clock ids
enum {
EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS,
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
EXT_CLK_VIDEO,
EXT_CLK_PSS_ALT_REF,
EXT_CLK_AUX_REF,
EXT_CLK_GT_CRX_REF,
EXT_CLK_SWDT0,
EXT_CLK_SWDT1,
zynqmp: pm: Fix clock models and IDs of GEM-related clocks GEM-related clock models were incorrect and are fixed as follows (documented below for GEM0, but the same holds for any GEM ID): - CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this clock is newly introduced in this patch. - CLK_GEM0_REF models the clock mux that selects the reference clock for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL. Note that the routing of external clock to the mux is not modelled and is assumed to be configured by the FSBL if required, and not changeable at runtime. The ID of this clock is introduced in this patch. - CLK_GEM0_TX models clock with only a gate that is controlled via bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID value of CLK_GEM0_REF. This is done in order to fix the clock models and incorrect binding without requiring to change device-tree (binding of clock IDs to GEM interface). - CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced from external RGMII PHY (via MIO or EMIO). We do not model the whole clock path to the Rx gate, since this is configured by the FSBL and never changed at runtime (and there is no mechanism to change the path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX were swapped in device tree, so by fixing the IDs this way there is no need for device tree fix. Rates of the external RX/TX clocks can be specified in device tree if needed. Right now, that's not necessary because Tx clock is sourced from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas the Rx clock is sourced from external reference and the driver never attempts to get/get clock rate (only to enable it). If this changes in future, ATF clock model doesn't need to be changed. Instead, the clock rates for gem0_tx_ext and gem0_rx_ext have to be specified in device tree. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <will.wong@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79
2018-09-17 13:25:16 +01:00
EXT_CLK_GEM0_TX_EMIO,
EXT_CLK_GEM1_TX_EMIO,
EXT_CLK_GEM2_TX_EMIO,
EXT_CLK_GEM3_TX_EMIO,
EXT_CLK_GEM0_RX_EMIO,
EXT_CLK_GEM1_RX_EMIO,
EXT_CLK_GEM2_RX_EMIO,
EXT_CLK_GEM3_RX_EMIO,
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
EXT_CLK_MIO50_OR_MIO51,
EXT_CLK_MIO0,
EXT_CLK_MIO1,
EXT_CLK_MIO2,
EXT_CLK_MIO3,
EXT_CLK_MIO4,
EXT_CLK_MIO5,
EXT_CLK_MIO6,
EXT_CLK_MIO7,
EXT_CLK_MIO8,
EXT_CLK_MIO9,
EXT_CLK_MIO10,
EXT_CLK_MIO11,
EXT_CLK_MIO12,
EXT_CLK_MIO13,
EXT_CLK_MIO14,
EXT_CLK_MIO15,
EXT_CLK_MIO16,
EXT_CLK_MIO17,
EXT_CLK_MIO18,
EXT_CLK_MIO19,
EXT_CLK_MIO20,
EXT_CLK_MIO21,
EXT_CLK_MIO22,
EXT_CLK_MIO23,
EXT_CLK_MIO24,
EXT_CLK_MIO25,
EXT_CLK_MIO26,
EXT_CLK_MIO27,
EXT_CLK_MIO28,
EXT_CLK_MIO29,
EXT_CLK_MIO30,
EXT_CLK_MIO31,
EXT_CLK_MIO32,
EXT_CLK_MIO33,
EXT_CLK_MIO34,
EXT_CLK_MIO35,
EXT_CLK_MIO36,
EXT_CLK_MIO37,
EXT_CLK_MIO38,
EXT_CLK_MIO39,
EXT_CLK_MIO40,
EXT_CLK_MIO41,
EXT_CLK_MIO42,
EXT_CLK_MIO43,
EXT_CLK_MIO44,
EXT_CLK_MIO45,
EXT_CLK_MIO46,
EXT_CLK_MIO47,
EXT_CLK_MIO48,
EXT_CLK_MIO49,
EXT_CLK_MIO50,
EXT_CLK_MIO51,
EXT_CLK_MIO52,
EXT_CLK_MIO53,
EXT_CLK_MIO54,
EXT_CLK_MIO55,
EXT_CLK_MIO56,
EXT_CLK_MIO57,
EXT_CLK_MIO58,
EXT_CLK_MIO59,
EXT_CLK_MIO60,
EXT_CLK_MIO61,
EXT_CLK_MIO62,
EXT_CLK_MIO63,
EXT_CLK_MIO64,
EXT_CLK_MIO65,
EXT_CLK_MIO66,
EXT_CLK_MIO67,
EXT_CLK_MIO68,
EXT_CLK_MIO69,
EXT_CLK_MIO70,
EXT_CLK_MIO71,
EXT_CLK_MIO72,
EXT_CLK_MIO73,
EXT_CLK_MIO74,
EXT_CLK_MIO75,
EXT_CLK_MIO76,
EXT_CLK_MIO77,
zynqmp: pm: Minor corrections for MISRA compliance Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-02-08 00:25:41 +00:00
END_OF_CLKS,
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
};
zynqmp: pm: Minor corrections for MISRA compliance Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-02-08 00:25:41 +00:00
#define CLK_MAX (unsigned int)(END_OF_CLKS)
//CLock types
#define CLK_TYPE_OUTPUT 0U
#define CLK_TYPE_EXTERNAL 1U
//Topology types
#define TYPE_INVALID 0U
#define TYPE_MUX 1U
#define TYPE_PLL 2U
#define TYPE_FIXEDFACTOR 3U
#define TYPE_DIV1 4U
#define TYPE_DIV2 5U
#define TYPE_GATE 6U
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
zynqmp: pm: Reimplement clock enable EEMI API Clock enable EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock enable API to trigger locking of the PLLs in the pm_clock_enable() implementation we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock that can be gated. For case 1) we'll call pm_api_clock_pll_enable() implemented in pm_api_clock.h/c. This function checks what is the buffered PLL mode and calls the system-level PLL set mode EEMI API with the buffered mode value specified as argument. Long term, if linux driver get fixed to use PLL EEMI API to control PLLs, this case could be removed from ATF. For case 2) we'll call the PMU to configure the clock gate. This is done using system-level clock enable EEMI API. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-04 19:45:59 +00:00
struct pm_pll;
struct pm_pll *pm_clock_get_pll(enum clock_id clock_id);
zynqmp: pm: Reimplement clock set parent EEMI API Clock set parent EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock set parent API to set pre_src, post_src, div2 and bypass, in the implementation of pm_clock_set_parent() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC, *_POST_SRC, *_INT_MUX or *PLL clock IDs); or 2) given clock ID is truly an on-chip clock. For case 1) we'll map the call onto PLL set parameter EEMI API with the respective parameter ID. Since clock set parent interface to EL1/2 receives parent index (mux select value), the value is just passed to PMU. Functions that appear to be unused after this change is made are removed. Setting the parent of *PLL clocks, that actually model bypass, is not possible. This is already ensured by the existing clock model having the CLK_SET_RATE_NO_REPARENT flag. The API also doesn't allow changing the bypass parent. Bypass is controlled only by the PMU firmware. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-04 19:57:40 +00:00
struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id);
zynqmp: pm: Reimplement clock get divider EEMI API Clock get divider EEMI API is reimplemented to use system-level clock get divider EEMI API rather than direct MMIO read/write accesses to clock control registers. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-04 19:53:37 +00:00
uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id);
zynqmp: pm: Add clock control EEMI API and ioctl functions These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:25 +00:00
enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
zynqmp: pm: Add API to get number of clocks Currently in Linux maximum number of clocks is hard-coded and so it needs to allocate static memory. It can get actual clock number after querying all clock names by special clock name string. Add new query data parameter to get actual number of clocks so Linux can get actual clock numbers in advance. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
2018-07-20 11:16:27 +01:00
enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks);
zynqmp: pm: Add clock control EEMI API and ioctl functions These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:25 +00:00
enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
unsigned int index,
uint32_t *topology);
enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id,
uint32_t *mul,
uint32_t *div);
enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id,
unsigned int index,
uint32_t *parents);
enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id,
uint32_t *attr);
zynqmp: pm_service: Add support to query max divisor Add new QID to get maximum supported divisor by clock. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I35fc92457e522f3f0614d983c21e55c2b0b8e80a
2019-03-19 19:43:21 +00:00
enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id,
uint8_t div_type,
uint32_t *max_div);
zynqmp: pm: Get PLL fractional data using PLL get parameter EEMI API Fractional data should be get using PLL get parameter EEMI API. This stands for system-level communication (APU to PMU). Since linux already uses a specific IOCTL function to do this and we need to keep it that way, the pll clock ID given by linux has to be mapped to the pll node ID that is communicated at the system-level (argument of PLL get parameter API). With this modification the function pm_api_clk_get_pll_frac_data is removed from pm_api_clock.c/h because it became unused. The clock enum is defined as 'enum clock_id'. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-02 20:40:17 +00:00
enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id,
enum pm_node_id *node_id);
zynqmp: pm: Reimplement clock enable EEMI API Clock enable EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock enable API to trigger locking of the PLLs in the pm_clock_enable() implementation we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock that can be gated. For case 1) we'll call pm_api_clock_pll_enable() implemented in pm_api_clock.h/c. This function checks what is the buffered PLL mode and calls the system-level PLL set mode EEMI API with the buffered mode value specified as argument. Long term, if linux driver get fixed to use PLL EEMI API to control PLLs, this case could be removed from ATF. For case 2) we'll call the PMU to configure the clock gate. This is done using system-level clock enable EEMI API. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-04 19:45:59 +00:00
enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id);
zynqmp: pm: Get PLL fractional data using PLL get parameter EEMI API Fractional data should be get using PLL get parameter EEMI API. This stands for system-level communication (APU to PMU). Since linux already uses a specific IOCTL function to do this and we need to keep it that way, the pll clock ID given by linux has to be mapped to the pll node ID that is communicated at the system-level (argument of PLL get parameter API). With this modification the function pm_api_clk_get_pll_frac_data is removed from pm_api_clock.c/h because it became unused. The clock enum is defined as 'enum clock_id'. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-02 20:40:17 +00:00
zynqmp: pm: Reimplement clock enable EEMI API Clock enable EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock enable API to trigger locking of the PLLs in the pm_clock_enable() implementation we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock that can be gated. For case 1) we'll call pm_api_clock_pll_enable() implemented in pm_api_clock.h/c. This function checks what is the buffered PLL mode and calls the system-level PLL set mode EEMI API with the buffered mode value specified as argument. Long term, if linux driver get fixed to use PLL EEMI API to control PLLs, this case could be removed from ATF. For case 2) we'll call the PMU to configure the clock gate. This is done using system-level clock enable EEMI API. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-04 19:45:59 +00:00
enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
zynqmp: pm: Reimplement clock disable EEMI API Clock disable EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock disable API to reset the PLL in the implementation of pm_clock_disable() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock that can be gated. For case 1) we'll call pm_api_clock_pll_disable() implemented in pm_api_clock.h/c. This function will reset the PLL using the system-level PLL set mode EEMI API with the reset mode argument. For case 2) we'll call the PMU to configure the clock gate. This is done using system-level clock disable EEMI API. Functions that appear to be unused after this change is made are removed. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-02 20:54:40 +00:00
enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll);
zynqmp: pm: Reimplement clock get state (status) EEMI API Clock get state EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux is_enabled method for PLLs still uses clock get state API get the PLL state, in the implementation of pm_clock_getstate() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock whose state of the gate should be returned. For case 1) we'll call pm_api_clock_pll_getstate() implemented in pm_api_clock.h/c. This function will query the PLL state from PMU using the system-level PLL get mode EEMI API. For case 2) we'll call the PMU to query the clock gate state using system-level clock get status EEMI API. Functions that appear to be unused after this change is made are removed. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-02 20:55:41 +00:00
enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
unsigned int *state);
zynqmp: pm: Reimplement clock set parent EEMI API Clock set parent EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock set parent API to set pre_src, post_src, div2 and bypass, in the implementation of pm_clock_set_parent() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC, *_POST_SRC, *_INT_MUX or *PLL clock IDs); or 2) given clock ID is truly an on-chip clock. For case 1) we'll map the call onto PLL set parameter EEMI API with the respective parameter ID. Since clock set parent interface to EL1/2 receives parent index (mux select value), the value is just passed to PMU. Functions that appear to be unused after this change is made are removed. Setting the parent of *PLL clocks, that actually model bypass, is not possible. This is already ensured by the existing clock model having the CLK_SET_RATE_NO_REPARENT flag. The API also doesn't allow changing the bypass parent. Bypass is controlled only by the PMU firmware. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-04 19:57:40 +00:00
enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll,
enum clock_id clock_id,
unsigned int parent_index);
zynqmp: pm: Reimplement clock get parent EEMI API Clock get parent EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock set parent API to get pre_src, post_src, div2 and bypasss, in the implementation of pm_clock_get_parent() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC, *_POST_SRC, *_INT_MUX or *_PLL clock IDs); or 2) given clock ID is truly an on-chip clock. For case 1) we'll map the call onto PLL-specific EEMI API with the respective parameter ID. For case 2) the call is passed to the PMU. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-02 21:44:25 +00:00
enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll,
enum clock_id clock_id,
unsigned int *parent_index);
zynqmp: pm: Buffer the PLL mode that is set using IOCTL API When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the fractional mode to be changed in hardware. Furthermore, even before this patch setting the mode which is done by writing into register takes no effect until the PLL reset is deasserted, i.e. until linux "enables" the PLL. To adjust the code to system-level PLL EEMI API and avoid unnecessary IPIs that would otherwise be issued, we buffer the mode value set via IOCTL until the PLL mode really needs to be set. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-02 20:46:46 +00:00
enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id,
unsigned int mode);
zynqmp: pm: Return the buffered PLL mode through IOCTL PLL get mode API When linux calls pm_ioctl_get_pll_frac_mode() it doesn't expect the actual mode to be read from hardware, but the value that it is intending to program. Therefore, we return the buffered value to linux. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-02 20:49:21 +00:00
enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id,
unsigned int *mode);
zynqmp: pm: Implement clock APIs - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-01-17 10:39:26 +00:00
Standardise header guards across codebase All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-08 10:20:19 +00:00
#endif /* PM_API_CLOCK_H */