2019-11-11 11:11:06 +00:00
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/utils_def.h>
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#ifndef FPGA_DEF_H
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#define FPGA_DEF_H
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/*
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* The initial FPGA image configures a system with 2 clusters, 1 core in each,
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* and multi-threading is unimplemented.
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*/
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#define FPGA_MAX_CLUSTER_COUNT 2
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#define FPGA_MAX_CPUS_PER_CLUSTER 1
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#define FPGA_MAX_PE_PER_CPU 1
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#define FPGA_PRIMARY_CPU 0x0
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/*******************************************************************************
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* FPGA image memory map related constants
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******************************************************************************/
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/* UART base address and clock frequency, as configured by the image */
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#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000
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#define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000
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#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
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#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ
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2019-12-02 13:33:40 +00:00
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#define FPGA_TIMER_FREQUENCY 10000000
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#define FPGA_TIMER_BASE 0x2a830000
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2019-11-11 11:11:06 +00:00
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#endif
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