2018-04-10 01:48:58 +01:00
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <denver.h>
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2017-01-05 09:04:40 +00:00
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#include <errno.h>
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2018-04-10 01:48:58 +01:00
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#include <lib/mmio.h>
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#include <mce_private.h>
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2017-01-05 09:04:40 +00:00
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#include <platform_def.h>
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#include <t194_nvg.h>
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2017-06-22 05:54:06 +01:00
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#include <tegra_private.h>
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2018-04-10 01:48:58 +01:00
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2017-08-16 13:12:00 +01:00
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#define ID_AFR0_EL1_CACHE_OPS_SHIFT 12
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#define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU
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2017-01-05 09:04:40 +00:00
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/*
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* Reports the major and minor version of this interface.
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*
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* NVGDATA[0:31]: SW(R) Minor Version
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* NVGDATA[32:63]: SW(R) Major Version
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*/
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uint64_t nvg_get_version(void)
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2018-04-10 01:48:58 +01:00
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{
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2017-09-20 10:18:56 +01:00
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nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION);
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2018-04-10 01:48:58 +01:00
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2017-01-05 09:04:40 +00:00
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return (uint64_t)nvg_get_result();
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}
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2018-04-10 01:48:58 +01:00
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2017-01-05 09:04:40 +00:00
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/*
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* Enable the perf per watt mode.
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*
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* NVGDATA[0]: SW(RW), 1 = enable perf per watt mode
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*/
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int32_t nvg_enable_power_perf_mode(void)
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{
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2017-09-20 10:18:56 +01:00
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nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
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2017-01-05 09:04:40 +00:00
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return 0;
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}
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/*
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* Disable the perf per watt mode.
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*
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* NVGDATA[0]: SW(RW), 0 = disable perf per watt mode
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*/
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int32_t nvg_disable_power_perf_mode(void)
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{
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2017-09-20 10:18:56 +01:00
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nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
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2017-01-05 09:04:40 +00:00
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return 0;
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}
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/*
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* Enable the battery saver mode.
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*
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* NVGDATA[2]: SW(RW), 1 = enable battery saver mode
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*/
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int32_t nvg_enable_power_saver_modes(void)
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{
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2017-09-20 10:18:56 +01:00
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nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
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2017-01-05 09:04:40 +00:00
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return 0;
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}
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/*
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* Disable the battery saver mode.
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*
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* NVGDATA[2]: SW(RW), 0 = disable battery saver mode
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*/
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int32_t nvg_disable_power_saver_modes(void)
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{
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2017-09-20 10:18:56 +01:00
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nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
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2018-04-10 01:48:58 +01:00
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return 0;
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}
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2017-01-05 09:04:40 +00:00
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/*
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* Set the expected wake time in TSC ticks for the next low-power state the
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* core enters.
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*
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* NVGDATA[0:31]: SW(RW), WAKE_TIME
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*/
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void nvg_set_wake_time(uint32_t wake_time)
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{
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/* time (TSC ticks) until the core is expected to get a wake event */
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2017-09-20 10:18:56 +01:00
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nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time);
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2017-01-05 09:04:40 +00:00
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}
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2018-04-10 01:48:58 +01:00
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/*
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* This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and
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* SYSTEM_CSTATE values.
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2017-01-05 09:04:40 +00:00
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*
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* NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE
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* NVGDATA[7]: SW(W), update cluster flag
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* NVGDATA[8:9]: SW(RW), CG_CSTATE
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* NVGDATA[15]: SW(W), update ccplex flag
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* NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE
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* NVGDATA[23]: SW(W), update system flag
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* NVGDATA[31]: SW(W), update wake mask flag
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* NVGDATA[32:63]: SW(RW), WAKE_MASK
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2018-04-10 01:48:58 +01:00
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*/
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2017-01-05 09:04:40 +00:00
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void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
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uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask)
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2018-04-10 01:48:58 +01:00
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{
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uint64_t val = 0;
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/* update CLUSTER_CSTATE? */
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2017-01-05 09:04:40 +00:00
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if (cluster != 0U) {
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val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) |
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CLUSTER_CSTATE_UPDATE_BIT;
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}
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2018-04-10 01:48:58 +01:00
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/* update CCPLEX_CSTATE? */
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2017-01-05 09:04:40 +00:00
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if (ccplex != 0U) {
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val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) |
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CCPLEX_CSTATE_UPDATE_BIT;
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}
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2018-04-10 01:48:58 +01:00
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/* update SYSTEM_CSTATE? */
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2017-01-05 09:04:40 +00:00
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if (system != 0U) {
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val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
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SYSTEM_CSTATE_UPDATE_BIT;
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}
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2018-04-10 01:48:58 +01:00
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/* update wake mask value? */
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2017-01-05 09:04:40 +00:00
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if (update_wake_mask != 0U) {
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2018-04-10 01:48:58 +01:00
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val |= CSTATE_WAKE_MASK_UPDATE_BIT;
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2017-01-05 09:04:40 +00:00
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}
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2018-04-10 01:48:58 +01:00
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/* set the wake mask */
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2017-01-05 09:04:40 +00:00
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val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT;
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2018-04-10 01:48:58 +01:00
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/* set the updated cstate info */
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2017-09-20 10:18:56 +01:00
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nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
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2018-04-10 01:48:58 +01:00
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}
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2017-01-05 09:04:40 +00:00
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/*
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* Return a non-zero value if the CCPLEX is able to enter SC7
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*
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* NVGDATA[0]: SW(R), Is allowed result
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*/
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int32_t nvg_is_sc7_allowed(void)
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2018-04-10 01:48:58 +01:00
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{
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2017-01-05 09:04:40 +00:00
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/* issue command to check if SC7 is allowed */
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2017-09-20 10:18:56 +01:00
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nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED);
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2017-01-05 09:04:40 +00:00
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/* 1 = SC7 allowed, 0 = SC7 not allowed */
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return (int32_t)nvg_get_result();
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2018-04-10 01:48:58 +01:00
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}
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2017-01-05 09:04:40 +00:00
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/*
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* Wake an offlined logical core. Note that a core is offlined by entering
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* a C-state where the WAKE_MASK is all 0.
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*
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* NVGDATA[0:3]: SW(W) logical core to online
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*/
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int32_t nvg_online_core(uint32_t core)
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2018-04-10 01:48:58 +01:00
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{
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2017-01-05 09:04:40 +00:00
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int32_t ret = 0;
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2018-04-10 01:48:58 +01:00
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2017-01-05 09:04:40 +00:00
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/* sanity check the core ID value */
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if (core > (uint32_t)PLATFORM_CORE_COUNT) {
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ERROR("%s: unknown core id (%d)\n", __func__, core);
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ret = EINVAL;
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} else {
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/* get a core online */
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2017-09-20 10:18:56 +01:00
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nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
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(uint64_t)core & MCE_CORE_ID_MASK);
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2018-04-10 01:48:58 +01:00
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}
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2017-01-05 09:04:40 +00:00
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return ret;
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}
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/*
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* MC GSC (General Security Carveout) register values are expected to be
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* changed by TrustZone ARM code after boot.
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*
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* NVGDATA[0:15] SW(R) GSC enun
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*/
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int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
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2018-04-10 01:48:58 +01:00
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{
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2017-09-29 11:09:17 +01:00
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int32_t ret;
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2017-01-05 09:04:40 +00:00
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/* sanity check GSC ID */
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2017-09-29 11:09:17 +01:00
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if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) {
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ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx);
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2017-01-05 09:04:40 +00:00
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ret = EINVAL;
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} else {
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2017-09-20 10:18:56 +01:00
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nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
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2017-01-05 09:04:40 +00:00
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(uint64_t)gsc_idx);
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2018-04-10 01:48:58 +01:00
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}
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2017-01-05 09:04:40 +00:00
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return ret;
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}
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2018-04-10 01:48:58 +01:00
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2017-01-05 09:04:40 +00:00
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/*
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* Cache clean operation for all CCPLEX caches.
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*/
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int32_t nvg_roc_clean_cache(void)
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{
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2017-08-16 13:12:00 +01:00
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int32_t ret = 0;
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2018-04-10 01:48:58 +01:00
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2017-08-16 13:12:00 +01:00
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/* check if cache flush through mts is supported */
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if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
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ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
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if (nvg_cache_clean() == 0U) {
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ERROR("%s: failed\n", __func__);
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ret = EINVAL;
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}
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} else {
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ret = EINVAL;
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}
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return ret;
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2018-04-10 01:48:58 +01:00
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}
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2017-01-05 09:04:40 +00:00
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/*
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* Cache clean and invalidate operation for all CCPLEX caches.
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*/
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int32_t nvg_roc_flush_cache(void)
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2018-04-10 01:48:58 +01:00
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{
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2017-08-16 13:12:00 +01:00
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int32_t ret = 0;
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2018-04-10 01:48:58 +01:00
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2017-08-16 13:12:00 +01:00
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/* check if cache flush through mts is supported */
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if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
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ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
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if (nvg_cache_clean_inval() == 0U) {
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ERROR("%s: failed\n", __func__);
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ret = EINVAL;
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}
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} else {
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ret = EINVAL;
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}
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return ret;
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2017-01-05 09:04:40 +00:00
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}
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2018-04-10 01:48:58 +01:00
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2017-01-05 09:04:40 +00:00
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/*
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* Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
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*/
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int32_t nvg_roc_clean_cache_trbits(void)
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{
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2017-08-16 13:12:00 +01:00
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int32_t ret = 0;
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2018-04-10 01:48:58 +01:00
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2017-08-16 13:12:00 +01:00
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/* check if cache flush through mts is supported */
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if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
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ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
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if (nvg_cache_inval_all() == 0U) {
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ERROR("%s: failed\n", __func__);
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ret = EINVAL;
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}
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} else {
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ret = EINVAL;
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}
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return ret;
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2018-04-10 01:48:58 +01:00
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}
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2017-01-05 09:04:40 +00:00
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/*
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* Set the power state for a core
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*/
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int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
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{
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int32_t ret = 0;
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2017-06-22 05:54:06 +01:00
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uint64_t val = 0ULL;
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2017-01-05 09:04:40 +00:00
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/* check for allowed power state */
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if ((state != (uint32_t)TEGRA_NVG_CORE_C0) &&
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(state != (uint32_t)TEGRA_NVG_CORE_C1) &&
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(state != (uint32_t)TEGRA_NVG_CORE_C6) &&
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(state != (uint32_t)TEGRA_NVG_CORE_C7))
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{
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ERROR("%s: unknown cstate (%d)\n", __func__, state);
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ret = EINVAL;
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} else {
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/* time (TSC ticks) until the core is expected to get a wake event */
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nvg_set_wake_time(wake_time);
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/* set the core cstate */
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2017-06-22 05:54:06 +01:00
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val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
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write_actlr_el1(val | (uint64_t)state);
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2017-01-05 09:04:40 +00:00
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}
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return ret;
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}
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