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arm-trusted-firmware/plat/nvidia/tegra/include/t186/tegra_def.h

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Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
/*
Tegra186: register FIQ interrupt sources This patch registers all the FIQ interrupt sources during platform setup. Currently we support AON and TOP watchdog timer interrupts. Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-12-29 02:12:59 +00:00
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __TEGRA_DEF_H__
#define __TEGRA_DEF_H__
Tegra186: move platform specific MCE defines to tegra_def.h This patch moves the MCE's configurable parameters to tegra_def.h for the Tegra186 SoC, to allow forward compatiblity. Change-Id: If8660c1c09908a4064dbb67d5ca4fb78389cab13 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-12-12 22:24:17 +00:00
/*******************************************************************************
* MCE apertures used by the ARI interface
*
* Aperture 0 - Cpu0 (ARM Cortex A-57)
* Aperture 1 - Cpu1 (ARM Cortex A-57)
* Aperture 2 - Cpu2 (ARM Cortex A-57)
* Aperture 3 - Cpu3 (ARM Cortex A-57)
* Aperture 4 - Cpu4 (Denver15)
* Aperture 5 - Cpu5 (Denver15)
******************************************************************************/
#define MCE_ARI_APERTURE_0_OFFSET 0x0
#define MCE_ARI_APERTURE_1_OFFSET 0x10000
#define MCE_ARI_APERTURE_2_OFFSET 0x20000
#define MCE_ARI_APERTURE_3_OFFSET 0x30000
#define MCE_ARI_APERTURE_4_OFFSET 0x40000
#define MCE_ARI_APERTURE_5_OFFSET 0x50000
#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
/* number of apertures */
#define MCE_ARI_APERTURES_MAX 6
/* each ARI aperture is 64KB */
#define MCE_ARI_APERTURE_SIZE 0x10000
/*******************************************************************************
* CPU core id macros for the MCE_ONLINE_CORE ARI
******************************************************************************/
#define MCE_CORE_ID_MAX 8
#define MCE_CORE_ID_MASK 0x7
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
/*******************************************************************************
Tegra186: support for C6/C7 CPU_SUSPEND states This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is an idle state while C7 is a powerdown state. The MCE block takes care of the entry/exit to/from these core power states and hence we call the corresponding MCE handler to process these requests. The NS driver passes the tentative time that the core is expected to stay in this state as part of the power_state parameter, which we store in a per-cpu array and pass it to the MCE block. Change-Id: I152acb11ab93d91fb866da2129b1795843dfa39b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-01-19 03:03:19 +00:00
* These values are used by the PSCI implementation during the `CPU_SUSPEND`
* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
* parameter.
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
******************************************************************************/
Tegra186: support for C6/C7 CPU_SUSPEND states This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is an idle state while C7 is a powerdown state. The MCE block takes care of the entry/exit to/from these core power states and hence we call the corresponding MCE handler to process these requests. The NS driver passes the tentative time that the core is expected to stay in this state as part of the power_state parameter, which we store in a per-cpu array and pass it to the MCE block. Change-Id: I152acb11ab93d91fb866da2129b1795843dfa39b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-01-19 03:03:19 +00:00
#define PSTATE_ID_CORE_IDLE 6
#define PSTATE_ID_CORE_POWERDN 7
#define PSTATE_ID_SOC_POWERDN 2
/*******************************************************************************
* Platform power states (used by PSCI framework)
*
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 8
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
/*******************************************************************************
* Implementation defined ACTLR_EL3 bit definitions
******************************************************************************/
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
ACTLR_EL3_L2ECTLR_BIT | \
ACTLR_EL3_L2CTLR_BIT | \
ACTLR_EL3_CPUECTLR_BIT | \
ACTLR_EL3_CPUACTLR_BIT)
Tegra186: register FIQ interrupt sources This patch registers all the FIQ interrupt sources during platform setup. Currently we support AON and TOP watchdog timer interrupts. Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-12-29 02:12:59 +00:00
/*******************************************************************************
* Secure IRQ definitions
******************************************************************************/
#define TEGRA186_TOP_WDT_IRQ 49
#define TEGRA186_AON_WDT_IRQ 50
#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
/*******************************************************************************
* Tegra Miscellanous register constants
******************************************************************************/
#define TEGRA_MISC_BASE 0x00100000
Tegra: memctrl_v2: implement MC txn override WAR This patch sets the Memory Controller's TXN_OVERRIDE registers for most write clients to CGID_ADR. This ensures ordering is maintained. In some cases WAW ordering problems could occur. There are different settings for Tegra version A01 v A02. Original changes by Alex Waterman <alexw@nvidia.com> Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-02-17 23:07:49 +00:00
#define HARDWARE_REVISION_OFFSET 0x4
Tegra186: enable support for simulation environment The Tegra simulation environment has limited capabilities. This patch checks the chip's major and minor versions to decide the features to enable/disable - MCE firmware version checking is disabled and limited Memory Controller settings are enabled Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-04-02 23:41:20 +01:00
Tegra186: implement support for System Suspend This patch adds the chip level support for System Suspend entry and exit. As part of the entry sequence we first query the MCE firmware to check if it is safe to enter system suspend. Once we get a green light, we save hardware block settings and enter the power state. As expected, all the hardware settings are restored once we exit the power state. Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-03-03 21:52:52 +00:00
#define MISCREG_PFCFG 0x200C
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
Tegra186: re-configure MSS' client settings This patch reprograms MSS to make ROC deal with ordering of MC traffic after boot and system suspend exit. This is needed as device boots with MSS having all control but POR wants ROC to deal with the ordering. Performance is expected to improve with ROC but since no one has really tested the performance, keep the option configurable for now by introducing a platform level makefile variable. Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-03-12 01:18:51 +00:00
/*******************************************************************************
* Tegra TSA Controller constants
******************************************************************************/
#define TEGRA_TSA_BASE 0x02400000
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
/*******************************************************************************
* Tegra Memory Controller constants
******************************************************************************/
#define TEGRA_MC_STREAMID_BASE 0x02C00000
#define TEGRA_MC_BASE 0x02C10000
/*******************************************************************************
* Tegra UART Controller constants
******************************************************************************/
#define TEGRA_UARTA_BASE 0x03100000
#define TEGRA_UARTB_BASE 0x03110000
#define TEGRA_UARTC_BASE 0x0C280000
#define TEGRA_UARTD_BASE 0x03130000
#define TEGRA_UARTE_BASE 0x03140000
#define TEGRA_UARTF_BASE 0x03150000
#define TEGRA_UARTG_BASE 0x0C290000
Tegra186: Enable ECC and Parity Protection for A02p SKUs This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot, for Tegra186 A02p SKUs. Change-Id: I8522a6cb61f5e4fa9e0471f558a0c3ee8078370e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-05-18 21:39:16 +01:00
/*******************************************************************************
* Tegra Fuse Controller related constants
******************************************************************************/
#define TEGRA_FUSE_BASE 0x03820000
#define OPT_SUBREVISION 0x248
#define SUBREVISION_MASK 0xFF
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
/*******************************************************************************
* GICv2 & interrupt handling related constants
******************************************************************************/
#define TEGRA_GICD_BASE 0x03881000
#define TEGRA_GICC_BASE 0x03882000
Tegra186: implement support for System Suspend This patch adds the chip level support for System Suspend entry and exit. As part of the entry sequence we first query the MCE firmware to check if it is safe to enter system suspend. Once we get a green light, we save hardware block settings and enter the power state. As expected, all the hardware settings are restored once we exit the power state. Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-03-03 21:52:52 +00:00
/*******************************************************************************
* Security Engine related constants
******************************************************************************/
#define TEGRA_SE0_BASE 0x03AC0000
#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
#define TEGRA_PKA1_BASE 0x03AD0000
#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
#define TEGRA_RNG1_BASE 0x03AE0000
#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
/*******************************************************************************
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE 0x05000000
/*******************************************************************************
* Tegra micro-seconds timer constants
******************************************************************************/
#define TEGRA_TMRUS_BASE 0x0C2E0000
/*******************************************************************************
* Tegra Power Mgmt Controller constants
******************************************************************************/
#define TEGRA_PMC_BASE 0x0C360000
/*******************************************************************************
* Tegra scratch registers constants
******************************************************************************/
#define TEGRA_SCRATCH_BASE 0x0C390000
Tegra186: implement support for System Suspend This patch adds the chip level support for System Suspend entry and exit. As part of the entry sequence we first query the MCE firmware to check if it is safe to enter system suspend. Once we get a green light, we save hardware block settings and enter the power state. As expected, all the hardware settings are restored once we exit the power state. Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-03-03 21:52:52 +00:00
#define SECURE_SCRATCH_RSV6 0x680
#define SECURE_SCRATCH_RSV11_LO 0x6A8
#define SECURE_SCRATCH_RSV11_HI 0x6AC
Tegra186: handlers to get BL31 arguments from previous bootloader This patch overrides the default handlers to get BL31 arguments from the previous bootloader. The previous bootloader stores the pointer to the arguments in PMC secure scratch register #53. BL31 is the first component running on the CPU, as there isn't a previous bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes that there are no input parameters passed by the previous bootloader. Change-Id: Idacc1df292a70c9c1cb4d5c3a774bd796175d5e8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-05-23 19:47:34 +01:00
#define SECURE_SCRATCH_RSV53_LO 0x7F8
#define SECURE_SCRATCH_RSV53_HI 0x7FC
Tegra: memctrl_v2: save TZDRAM settings to secure scratch registers Save TZDRAM settings for SC7 resume firmware to restore. SECURITY_BOM: MC_SECURITY_CFG0_0 = SECURE_RSV55_SCRATCH_0 SECURITY_BOM_HI: MC_SECURITY_CFG3_0 = SECURE_RSV55_SCRATCH_1 SECURITY_SIZE_MB: MC_SECURITY_CFG1_0 = SECURE_RSV54_SCRATCH_1 Change-Id: I78e891d9ebf576ff2a17ff87cf3aff4030ee11b8 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-07-29 13:10:59 +01:00
#define SECURE_SCRATCH_RSV54_HI 0x804
#define SECURE_SCRATCH_RSV55_LO 0x808
#define SECURE_SCRATCH_RSV55_HI 0x80C
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
/*******************************************************************************
* Tegra Memory Mapped Control Register Access Bus constants
******************************************************************************/
#define TEGRA_MMCRAB_BASE 0x0E000000
/*******************************************************************************
* Tegra SMMU Controller constants
******************************************************************************/
#define TEGRA_SMMU_BASE 0x12000000
Tegra: memctrl_v2: secure the on-chip TZSRAM memory This patch programs the Memory controller's control registers to disable non-secure accesses to the TZRAM. In case these registers are already programmed by the BL2/BL30, then the driver just bails out. Change-Id: Ia1416988050e3d067296373060c717a260499122 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-12-30 23:15:08 +00:00
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
#define TEGRA_TZRAM_BASE 0x30000000
Tegra: memctrl_v2: TZRAM aperture configuration settings This patch enables the configuration settings for the TZRAM aperture by programming the base/size of the aperture and restricting access to it. We allow only the CPU to read/write by programming the access configuration registers to 0. Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-05-26 00:35:04 +01:00
#define TEGRA_TZRAM_SIZE 0x40000
Tegra: memctrl_v2: secure the on-chip TZSRAM memory This patch programs the Memory controller's control registers to disable non-secure accesses to the TZRAM. In case these registers are already programmed by the BL2/BL30, then the driver just bails out. Change-Id: Ia1416988050e3d067296373060c717a260499122 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-12-30 23:15:08 +00:00
Tegra186: platform support for Tegra "T186" SoC Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-08-25 12:33:14 +01:00
#endif /* __TEGRA_DEF_H__ */