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Merge changes I80661161,I82c1fa93,I018ccbb9,Ibc23734d,I97406abe, ... into integration 

* changes:
  feat(intel): add SMC support for HWMON voltage and temp sensor
  feat(intel): add SMC support for Get USERCODE
  fix(intel): extend SDM command to return the SDM firmware version
  feat(intel): add SMC for enquiring firmware version
  fix(intel): configuration status based on start request
  fix(intel): bit-wise configuration flag handling
  fix(intel): get config status OK status
  fix(intel): use macro as return value
  fix(intel): fix fpga config write return mechanism
  feat(intel): add SiP service for DCMF status
  feat(intel): add RSU 'Max Retry' SiP SMC services
  feat(intel): enable SMC SoC FPGA bridges enable/disable
  feat(intel): add SMC/PSCI services for DCMF version support
  feat(intel): allow to access all register addresses if DEBUG=1
  fix(intel): modify how configuration type is handled
  feat(intel): support SiP SVC version
  feat(intel): enable firewall for OCRAM in BL31
  feat(intel): create source file for firewall configuration
  fix(intel): refactor NOC header
This commit is contained in:
Manish Pandey 2022-04-28 18:51:50 +02:00 committed by TrustedFirmware Code Review
parent 9b9a21f297 52cf9c2cd4
commit 942b039221
15 changed files with 391 additions and 116 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
plat/intel/soc/agilex/bl31_plat_setup.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -14,6 +14,7 @@
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables.h>
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
@ -114,6 +115,8 @@ void bl31_platform_setup(void)
(uint64_t)plat_secondary_cpus_bl31_entry);
mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
ncore_enable_ocram_firewall();
}
const mmap_region_t plat_agilex_mmap[] = {

2
plat/intel/soc/agilex/include/agilex_noc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

2
plat/intel/soc/agilex/include/socfpga_plat_def.h
View File

@ -19,6 +19,8 @@
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
#define SOCFPGA_MMC_REG_BASE 0xff808000
#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000

6
plat/intel/soc/agilex/platform.mk
View File

@ -26,6 +26,7 @@ PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S \
plat/intel/soc/common/drivers/ccu/ncore_ccu.c \
plat/intel/soc/common/socfpga_delay_timer.c
BL2_SOURCES += \
@ -48,13 +49,12 @@ BL2_SOURCES += \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_emac.c \
plat/intel/soc/common/soc/socfpga_firewall.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c \
plat/intel/soc/common/soc/socfpga_system_manager.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c \
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
plat/intel/soc/common/drivers/wdt/watchdog.c
BL31_SOURCES += \
drivers/arm/cci/cci.c \

1
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
View File

@ -118,6 +118,7 @@ void ncore_enable_ocram_firewall(void)
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
}
uint32_t init_ncore_ccu(void)
{
uint32_t status;

12
plat/intel/soc/common/include/socfpga_mailbox.h
View File

@ -42,6 +42,7 @@
#define MBOX_CMD_CANCEL 0x03
#define MBOX_CMD_VAB_SRC_CERT 0x0B
#define MBOX_CMD_GET_IDCODE 0x10
#define MBOX_CMD_GET_USERCODE 0x13
#define MBOX_CMD_REBOOT_HPS 0x47
/* Reconfiguration Commands */
@ -50,6 +51,11 @@
#define MBOX_RECONFIG_DATA 0x08
#define MBOX_RECONFIG_STATUS 0x09
/* HWMON Commands */
#define MBOX_HWMON_READVOLT 0x18
#define MBOX_HWMON_READTEMP 0x19
/* QSPI Commands */
#define MBOX_CMD_QSPI_OPEN 0x32
#define MBOX_CMD_QSPI_CLOSE 0x33
@ -145,6 +151,10 @@
#define RSU_VERSION_ACMF BIT(8)
#define RSU_VERSION_ACMF_MASK 0xff00
/* Config Status Macros */
#define CONFIG_STATUS_WORD_SIZE 16U
#define CONFIG_STATUS_FW_VER_OFFSET 1
#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF
/* Mailbox Function Definitions */
@ -173,5 +183,7 @@ int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_rsu_update(uint32_t *flash_offset);
int mailbox_hps_stage_notify(uint32_t execution_stage);
int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
#endif /* SOCFPGA_MBOX_H */

95
plat/intel/soc/common/include/socfpga_noc.h Normal file
View File

@ -0,0 +1,95 @@
/*
* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SOCFPGA_NOC_H
#define SOCFPGA_NOC_H
/* Macros */
#define SCR_AXI_AP_MASK BIT(24)
#define SCR_FPGA2SOC_MASK BIT(16)
#define SCR_MPU_MASK BIT(0)
#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \
| SCR_MPU_MASK)
#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
#define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \
+ (SOCFPGA_CCU_NOC_##_ctrl##_##_dev))
#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \
+ (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \
+ (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
/* L3 Interconnect Register Map */
#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000
#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004
#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c
#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028
#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c
#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030
#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034
#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040
#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044
#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060
#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064
#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068
#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c
#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070
#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020
#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030
#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034
#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038
#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040
#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044
#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048
#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054
#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058
#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060
#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074
#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078
#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090
#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094
/* CCU NOC Register Map */
#define SOCFPGA_CCU_NOC_CPU0_RAM0 0x04688
#define SOCFPGA_CCU_NOC_IOM_RAM0 0x18628
#define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0)
#define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1)
/* Function Definitions */
void enable_ns_peripheral_access(void);
void enable_ns_bridge_access(void);
void enable_ns_ocram_access(void);
void enable_ocram_firewall(void);
#endif

34
plat/intel/soc/common/include/socfpga_sip_svc.h
View File

@ -27,6 +27,12 @@
#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
/* FPGA Bitstream Flag */
#define FLAG_PARTIAL_CONFIG BIT(0)
#define FLAG_AUTHENTICATION BIT(1)
#define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \
== FLAG_##_type)
/* Secure Register Access */
#define INTEL_SIP_SMC_REG_READ 0xC2000007
#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
@ -39,7 +45,16 @@
#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
#define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012
#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013
#define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014
#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015
/* Hardware monitor */
#define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020
#define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021
#define TEMP_CHANNEL_MAX (1 << 15)
#define VOLT_CHANNEL_MAX (1 << 15)
/* ECC */
#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
@ -49,24 +64,31 @@
/* Send Mailbox Command */
#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
#define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F
#define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032
/* Mailbox Command */
#define INTEL_SIP_SMC_GET_USERCODE 0xC200003D
/* SiP Definitions */
/* ECC DBE */
#define WARM_RESET_WFI_FLAG BIT(31)
#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
SYSMGR_ECC_DDR0_MASK |\
SYSMGR_ECC_DDR1_MASK)
/* Non-mailbox SMC Call */
#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
/* SMC function IDs for SiP Service queries */
#define SIP_SVC_CALL_COUNT 0x8200ff00
#define SIP_SVC_UID 0x8200ff01
#define SIP_SVC_VERSION 0x8200ff03
#define SIP_SVC_CALL_COUNT 0x8200ff00
#define SIP_SVC_UID 0x8200ff01
#define SIP_SVC_VERSION 0x8200ff03
/* SiP Service Calls version numbers */
#define SIP_SVC_VERSION_MAJOR 0
#define SIP_SVC_VERSION_MINOR 1
#define SIP_SVC_VERSION_MAJOR 1
#define SIP_SVC_VERSION_MINOR 0
/* Structure Definitions */

72
plat/intel/soc/common/include/socfpga_system_manager.h
View File

@ -42,13 +42,6 @@
#define IDLE_DATA_SOC2FPGA BIT(4)
#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
#define SCR_AXI_AP_MASK BIT(24)
#define SCR_FPGA2SOC_MASK BIT(16)
#define SCR_MPU_MASK BIT(0)
#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \
| SCR_MPU_MASK)
#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
#define SYSMGR_ECC_OCRAM_MASK BIT(1)
#define SYSMGR_ECC_DDR0_MASK BIT(16)
#define SYSMGR_ECC_DDR1_MASK BIT(17)
@ -58,69 +51,4 @@
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg))
#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \
+ (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \
+ (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
/* L3 Interconnect Register Map */
#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000
#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004
#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c
#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028
#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c
#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030
#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034
#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040
#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044
#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060
#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064
#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068
#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c
#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070
#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020
#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030
#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034
#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038
#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040
#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044
#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048
#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054
#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058
#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060
#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074
#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078
#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090
#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094
#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
void enable_ns_peripheral_access(void);
void enable_ns_bridge_access(void);
#endif /* SOCFPGA_SYSTEMMANAGER_H */

24
plat/intel/soc/common/soc/socfpga_system_manager.c → plat/intel/soc/common/soc/socfpga_firewall.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,6 +7,8 @@
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include "socfpga_noc.h"
#include "socfpga_plat_def.h"
#include "socfpga_system_manager.h"
void enable_nonsecure_access(void)
@ -92,16 +94,30 @@ void enable_ns_peripheral_access(void)
mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL);
#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
mmio_clrbits_32(SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
mmio_clrbits_32(SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
enable_ns_ocram_access();
mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3));
#endif
}
void enable_ns_ocram_access(void)
{
mmio_clrbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0),
SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK);
mmio_clrbits_32(SOCFPGA_CCU_NOC(IOM, RAM0),
SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK);
}
void enable_ns_bridge_access(void)
{
mmio_write_32(SOCFPGA_SOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL);
mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL);
}
void enable_ocram_firewall(void)
{
mmio_setbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0),
SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK);
mmio_setbits_32(SOCFPGA_CCU_NOC(IOM, RAM0),
SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK);
}

25
plat/intel/soc/common/soc/socfpga_mailbox.c
View File

@ -507,11 +507,13 @@ int intel_mailbox_get_config_status(uint32_t cmd, bool init_done)
return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
}
if ((res & SOFTFUNC_STATUS_CONF_DONE) == 0U)
if ((res & SOFTFUNC_STATUS_CONF_DONE) == 0U) {
return MBOX_CFGSTAT_STATE_CONFIG;
}
if (init_done && (res & SOFTFUNC_STATUS_INIT_DONE) == 0U)
if (init_done && (res & SOFTFUNC_STATUS_INIT_DONE) == 0U) {
return MBOX_CFGSTAT_STATE_CONFIG;
}
return MBOX_RET_OK;
}
@ -527,3 +529,22 @@ int intel_mailbox_is_fpga_not_ready(void)
return ret;
}
int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf)
{
unsigned int resp_len = sizeof(resp_buf);
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HWMON_READTEMP, &chan, 1U,
CMD_CASUAL, resp_buf,
&resp_len);
}
int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf)
{
unsigned int resp_len = sizeof(resp_buf);
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HWMON_READVOLT, &chan, 1U,
CMD_CASUAL, resp_buf,
&resp_len);
}

217
plat/intel/soc/common/socfpga_sip_svc.c
View File

@ -20,10 +20,17 @@
#define FPGA_CONFIG_BUFFER_SIZE 4
static int current_block, current_buffer;
static int read_block, max_blocks, is_partial_reconfig;
static int read_block, max_blocks;
static uint32_t send_id, rcv_id;
static uint32_t bytes_per_block, blocks_submitted;
static bool bridge_disable;
/* RSU static variables */
static uint32_t rsu_dcmf_ver[4] = {0};
/* RSU Max Retry */
static uint32_t rsu_max_retry;
static uint16_t rsu_dcmf_stat[4] = {0};
/* SiP Service UUID */
DEFINE_SVC_UUID2(intl_svc_uid,
@ -83,22 +90,23 @@ static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type)
{
uint32_t ret;
if (query_type == 1)
if (query_type == 1U) {
ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false);
else
} else {
ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true);
if (ret) {
if (ret == MBOX_CFGSTAT_STATE_CONFIG)
return INTEL_SIP_SMC_STATUS_BUSY;
else
return INTEL_SIP_SMC_STATUS_ERROR;
}
if (query_type != 1) {
/* full reconfiguration */
if (!is_partial_reconfig)
socfpga_bridges_enable(); /* Enable bridge */
if (ret != 0U) {
if (ret == MBOX_CFGSTAT_STATE_CONFIG) {
return INTEL_SIP_SMC_STATUS_BUSY;
} else {
return INTEL_SIP_SMC_STATUS_ERROR;
}
}
if (bridge_disable) {
socfpga_bridges_enable(); /* Enable bridge */
bridge_disable = false;
}
return INTEL_SIP_SMC_STATUS_OK;
@ -184,7 +192,7 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr,
return status;
}
static int intel_fpga_config_start(uint32_t config_type)
static int intel_fpga_config_start(uint32_t flag)
{
uint32_t argument = 0x1;
uint32_t response[3];
@ -192,7 +200,14 @@ static int intel_fpga_config_start(uint32_t config_type)
unsigned int size = 0;
unsigned int resp_len = ARRAY_SIZE(response);
is_partial_reconfig = config_type;
if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
bridge_disable = true;
}
if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
size = 1;
bridge_disable = false;
}
mailbox_clear_response();
@ -202,8 +217,10 @@ static int intel_fpga_config_start(uint32_t config_type)
status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
CMD_CASUAL, response, &resp_len);
if (status < 0)
return status;
if (status < 0) {
bridge_disable = false;
return INTEL_SIP_SMC_STATUS_ERROR;
}
max_blocks = response[0];
bytes_per_block = response[1];
@ -222,13 +239,12 @@ static int intel_fpga_config_start(uint32_t config_type)
read_block = 0;
current_buffer = 0;
/* full reconfiguration */
if (!is_partial_reconfig) {
/* Disable bridge */
/* Disable bridge on full reconfiguration */
if (bridge_disable) {
socfpga_bridges_disable();
}
return 0;
return INTEL_SIP_SMC_STATUS_OK;
}
static bool is_fpga_config_buffer_full(void)
@ -261,8 +277,9 @@ static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
intel_fpga_sdm_write_all();
if (!is_address_in_ddr_range(mem, size) ||
is_fpga_config_buffer_full())
is_fpga_config_buffer_full()) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
@ -279,14 +296,19 @@ static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
}
}
if (is_fpga_config_buffer_full())
if (is_fpga_config_buffer_full()) {
return INTEL_SIP_SMC_STATUS_BUSY;
}
return INTEL_SIP_SMC_STATUS_OK;
}
static int is_out_of_sec_range(uint64_t reg_addr)
{
#if DEBUG
return 0;
#endif
switch (reg_addr) {
case(0xF8011100): /* ECCCTRL1 */
case(0xF8011104): /* ECCCTRL2 */
@ -393,7 +415,77 @@ static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
return INTEL_SIP_SMC_STATUS_OK;
}
static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0,
uint64_t dcmf_ver_3_2)
{
rsu_dcmf_ver[0] = dcmf_ver_1_0;
rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32;
rsu_dcmf_ver[2] = dcmf_ver_3_2;
rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32;
return INTEL_SIP_SMC_STATUS_OK;
}
static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat)
{
rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16));
rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16));
rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16));
rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16));
return INTEL_SIP_SMC_STATUS_OK;
}
/* Intel HWMON services */
static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)
{
if (chan > TEMP_CHANNEL_MAX) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
if (mailbox_hwmon_readtemp(chan, retval) < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
return INTEL_SIP_SMC_STATUS_OK;
}
static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)
{
if (chan > VOLT_CHANNEL_MAX) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
if (mailbox_hwmon_readvolt(chan, retval) < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
return INTEL_SIP_SMC_STATUS_OK;
}
/* Mailbox services */
static uint32_t intel_smc_fw_version(uint32_t *fw_version)
{
int status;
unsigned int resp_len = CONFIG_STATUS_WORD_SIZE;
uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U};
status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
CMD_CASUAL, resp_data, &resp_len);
if (status < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
*fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK;
return INTEL_SIP_SMC_STATUS_OK;
}
static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
unsigned int len,
uint32_t urgent, uint32_t *response,
@ -419,6 +511,33 @@ static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
return INTEL_SIP_SMC_STATUS_OK;
}
static int intel_smc_get_usercode(uint32_t *user_code)
{
int status;
unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE;
status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
0U, CMD_CASUAL, user_code, &resp_len);
if (status < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
return INTEL_SIP_SMC_STATUS_OK;
}
/* Miscellaneous HPS services */
static uint32_t intel_hps_set_bridges(uint64_t enable)
{
if (enable != 0U) {
socfpga_bridges_enable();
} else {
socfpga_bridges_disable();
}
return INTEL_SIP_SMC_STATUS_OK;
}
/*
* This function is responsible for handling all SiP calls from the NS world
*/
@ -531,10 +650,41 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
SMC_RET2(handle, status, retval);
}
case INTEL_SIP_SMC_RSU_DCMF_VERSION:
SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0],
((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]);
case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION:
status = intel_rsu_copy_dcmf_version(x1, x2);
SMC_RET1(handle, status);
case INTEL_SIP_SMC_RSU_DCMF_STATUS:
SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK,
((uint64_t)rsu_dcmf_stat[3] << 48) |
((uint64_t)rsu_dcmf_stat[2] << 32) |
((uint64_t)rsu_dcmf_stat[1] << 16) |
rsu_dcmf_stat[0]);
case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS:
status = intel_rsu_copy_dcmf_status(x1);
SMC_RET1(handle, status);
case INTEL_SIP_SMC_RSU_MAX_RETRY:
SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry);
case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY:
rsu_max_retry = x1;
SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
case INTEL_SIP_SMC_ECC_DBE:
status = intel_ecc_dbe_notification(x1);
SMC_RET1(handle, status);
case INTEL_SIP_SMC_FIRMWARE_VERSION:
status = intel_smc_fw_version(&retval);
SMC_RET2(handle, status, retval);
case INTEL_SIP_SMC_MBOX_SEND_CMD:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
@ -543,11 +693,32 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
&len_in_resp);
SMC_RET3(handle, status, mbox_status, len_in_resp);
case INTEL_SIP_SMC_GET_USERCODE:
status = intel_smc_get_usercode(&retval);
SMC_RET2(handle, status, retval);
case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
&mbox_error);
SMC_RET4(handle, status, mbox_error, x1, retval64);
case INTEL_SIP_SMC_SVC_VERSION:
SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
SIP_SVC_VERSION_MAJOR,
SIP_SVC_VERSION_MINOR);
case INTEL_SIP_SMC_HPS_SET_BRIDGES:
status = intel_hps_set_bridges(x1);
SMC_RET1(handle, status);
case INTEL_SIP_SMC_HWMON_READTEMP:
status = intel_hwmon_readtemp(x1, &retval);
SMC_RET2(handle, status, retval);
case INTEL_SIP_SMC_HWMON_READVOLT:
status = intel_hwmon_readvolt(x1, &retval);
SMC_RET2(handle, status, retval);
default:
return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
cookie, handle, flags);

5
plat/intel/soc/stratix10/bl31_plat_setup.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,6 +17,7 @@
#include <platform_def.h>
#include "socfpga_mailbox.h"
#include "socfpga_noc.h"
#include "socfpga_private.h"
#include "socfpga_reset_manager.h"
#include "socfpga_system_manager.h"
@ -122,6 +123,8 @@ void bl31_platform_setup(void)
(uint64_t)plat_secondary_cpus_bl31_entry);
mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
enable_ocram_firewall();
}
const mmap_region_t plat_stratix10_mmap[] = {

3
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View File

@ -1,5 +1,4 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -19,6 +18,8 @@
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
#define SOCFPGA_MMC_REG_BASE 0xff808000
#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000

4
plat/intel/soc/stratix10/platform.mk
View File

@ -26,7 +26,8 @@ PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S \
plat/intel/soc/common/socfpga_delay_timer.c
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/soc/socfpga_firewall.c
BL2_SOURCES += \
common/desc_image_load.c \
@ -50,7 +51,6 @@ BL2_SOURCES += \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c \
plat/intel/soc/common/soc/socfpga_system_manager.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c