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Merge changes from topic "tegra-downstream-092319" into integration 

* changes:
  Tegra194: remove L2 ECC parity protection setting
  Tegra194: sip_calls: mark unused parameter as const
  Tegra194: implement handler to retrieve power domain tree
  Tegra194: mce: fix function declaration conflicts
  Tegra194: add macros to read GPU reset status
  Tegra194: skip notifying MCE in fake system suspend
  Tegra194: Enable system suspend
This commit is contained in:
Sandrine Bailleux 2019-11-19 08:05:08 +00:00 committed by TrustedFirmware Code Review
parent 896add4f1d d191573e6a
commit af1ac83e0f
5 changed files with 40 additions and 42 deletions
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2
plat/nvidia/tegra/include/t194/tegra_def.h
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@ -232,5 +232,7 @@
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE 0x200000000
#define TEGRA_GPU_RESET_REG_OFFSET 0x18UL
#define GPU_RESET_BIT (1UL << 0)
#endif /* __TEGRA_DEF_H__ */

6
plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
View File

@ -25,7 +25,7 @@
/*******************************************************************************
* Common handler for all MCE commands
******************************************************************************/
int32_t mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
uint64_t arg2)
{
uint64_t ret64 = 0, arg3, arg4, arg5;
@ -161,7 +161,7 @@ int32_t mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
break;
default:
ERROR("unknown MCE command (%lld)\n", cmd);
ERROR("unknown MCE command (%llu)\n", cmd);
ret = EINVAL;
break;
}
@ -196,7 +196,7 @@ int32_t mce_update_gsc_tzram(void)
/*******************************************************************************
* Handler to issue the UPDATE_CSTATE_INFO request
******************************************************************************/
void mce_update_cstate_info(mce_cstate_info_t *cstate)
void mce_update_cstate_info(const mce_cstate_info_t *cstate)
{
/* issue the UPDATE_CSTATE_INFO request */
nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system,

27
plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
View File

@ -18,9 +18,12 @@
#include <smmu.h>
#include <string.h>
#include <tegra_private.h>
#include <t194_nvg.h>
extern void prepare_core_pwr_dwn(void);
extern uint8_t tegra_fake_system_suspend;
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
extern void tegra186_cpu_reset_handler(void);
extern uint32_t __tegra186_cpu_reset_handler_data,
@ -93,6 +96,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
uint64_t smmu_ctx_base;
#endif
uint32_t val;
mce_cstate_info_t cstate_info = { 0 };
/* get the state ID */
pwr_domain_state = target_state->pwr_domain_state;
@ -131,7 +135,28 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
tegra_smmu_save_context(0);
#endif
/* Instruct the MCE to enter system suspend state */
if (tegra_fake_system_suspend == 0U) {
/* Prepare for system suspend */
cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6;
cstate_info.system = TEGRA_NVG_SYSTEM_SC7;
cstate_info.system_state_force = 1;
cstate_info.update_wake_mask = 1;
mce_update_cstate_info(&cstate_info);
do {
val = mce_command_handler(
MCE_CMD_IS_SC7_ALLOWED,
TEGRA_NVG_CORE_C7,
MCE_CORE_SLEEP_TIME_INFINITE,
0);
} while (val == 0);
/* Instruct the MCE to enter system suspend state */
(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);
}
}
return PSCI_E_SUCCESS;

45
plat/nvidia/tegra/soc/t194/plat_setup.c
View File

@ -25,9 +25,6 @@
#include <tegra_private.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
extern uint64_t tegra_enable_l2_ecc_parity_prot;
/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
* single root node. The first entry in the power domain descriptor specifies
@ -45,6 +42,14 @@ const unsigned char tegra_power_domain_tree_desc[] = {
PLATFORM_MAX_CPUS_PER_CLUSTER
};
/*******************************************************************************
* This function returns the Tegra default topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return tegra_power_domain_tree_desc;
}
/*
* Table of regions to map using the MMU.
*/
@ -137,49 +142,15 @@ uint32_t plat_get_console_from_id(int id)
return tegra186_uart_addresses[id];
}
/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */
#define TEGRA186_VER_A02P 0x1201
/*******************************************************************************
* Handler for early platform setup
******************************************************************************/
void plat_early_platform_setup(void)
{
int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
uint32_t chip_subrev, val;
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
/*
* Enable ECC and Parity Protection for Cortex-A57 CPUs
* for Tegra A02p SKUs
*/
if (impl != DENVER_IMPL) {
/* get the major, minor and sub-version values */
chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) &
SUBREVISION_MASK;
/* prepare chip version number */
val = (tegra_get_chipid_major() << 12) |
(tegra_get_chipid_minor() << 8) |
chip_subrev;
/* enable L2 ECC for Tegra186 A02P and beyond */
if (val >= TEGRA186_VER_A02P) {
val = read_l2ctlr_el1();
val |= L2_ECC_PARITY_PROTECTION_BIT;
write_l2ctlr_el1(val);
/*
* Set the flag to enable ECC/Parity Protection
* when we exit System Suspend or Cluster Powerdn
*/
tegra_enable_l2_ecc_parity_prot = 1;
}
}
}
/* Secure IRQs for Tegra186 */

2
plat/nvidia/tegra/soc/t194/plat_sip_calls.c
View File

@ -51,7 +51,7 @@ int plat_sip_handler(uint32_t smc_fid,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
const void *cookie,
void *handle,
uint64_t flags)
{