Merge changes from topic "tegra-downstream-092319" into integration
* changes: Tegra194: remove L2 ECC parity protection setting Tegra194: sip_calls: mark unused parameter as const Tegra194: implement handler to retrieve power domain tree Tegra194: mce: fix function declaration conflicts Tegra194: add macros to read GPU reset status Tegra194: skip notifying MCE in fake system suspend Tegra194: Enable system suspend
This commit is contained in:
commit
af1ac83e0f
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@ -232,5 +232,7 @@
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* Tegra Clock and Reset Controller constants
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE 0x200000000
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#define TEGRA_CAR_RESET_BASE 0x200000000
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#define TEGRA_GPU_RESET_REG_OFFSET 0x18UL
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#define GPU_RESET_BIT (1UL << 0)
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#endif /* __TEGRA_DEF_H__ */
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#endif /* __TEGRA_DEF_H__ */
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@ -25,7 +25,7 @@
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/*******************************************************************************
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/*******************************************************************************
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* Common handler for all MCE commands
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* Common handler for all MCE commands
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******************************************************************************/
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******************************************************************************/
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int32_t mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
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int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
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uint64_t arg2)
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uint64_t arg2)
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{
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{
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uint64_t ret64 = 0, arg3, arg4, arg5;
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uint64_t ret64 = 0, arg3, arg4, arg5;
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@ -161,7 +161,7 @@ int32_t mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
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break;
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break;
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default:
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default:
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ERROR("unknown MCE command (%lld)\n", cmd);
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ERROR("unknown MCE command (%llu)\n", cmd);
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ret = EINVAL;
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ret = EINVAL;
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break;
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break;
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}
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}
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@ -196,7 +196,7 @@ int32_t mce_update_gsc_tzram(void)
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/*******************************************************************************
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/*******************************************************************************
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* Handler to issue the UPDATE_CSTATE_INFO request
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* Handler to issue the UPDATE_CSTATE_INFO request
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******************************************************************************/
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******************************************************************************/
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void mce_update_cstate_info(mce_cstate_info_t *cstate)
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void mce_update_cstate_info(const mce_cstate_info_t *cstate)
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{
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{
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/* issue the UPDATE_CSTATE_INFO request */
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/* issue the UPDATE_CSTATE_INFO request */
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nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system,
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nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system,
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@ -18,9 +18,12 @@
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#include <smmu.h>
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#include <smmu.h>
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#include <string.h>
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#include <string.h>
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#include <tegra_private.h>
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#include <tegra_private.h>
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#include <t194_nvg.h>
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extern void prepare_core_pwr_dwn(void);
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extern void prepare_core_pwr_dwn(void);
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extern uint8_t tegra_fake_system_suspend;
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#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
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#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
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extern void tegra186_cpu_reset_handler(void);
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extern void tegra186_cpu_reset_handler(void);
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extern uint32_t __tegra186_cpu_reset_handler_data,
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extern uint32_t __tegra186_cpu_reset_handler_data,
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@ -93,6 +96,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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uint64_t smmu_ctx_base;
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uint64_t smmu_ctx_base;
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#endif
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#endif
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uint32_t val;
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uint32_t val;
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mce_cstate_info_t cstate_info = { 0 };
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/* get the state ID */
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/* get the state ID */
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pwr_domain_state = target_state->pwr_domain_state;
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pwr_domain_state = target_state->pwr_domain_state;
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@ -131,7 +135,28 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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tegra_smmu_save_context(0);
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tegra_smmu_save_context(0);
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#endif
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#endif
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if (tegra_fake_system_suspend == 0U) {
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/* Prepare for system suspend */
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cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6;
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cstate_info.system = TEGRA_NVG_SYSTEM_SC7;
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cstate_info.system_state_force = 1;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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do {
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val = mce_command_handler(
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MCE_CMD_IS_SC7_ALLOWED,
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TEGRA_NVG_CORE_C7,
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MCE_CORE_SLEEP_TIME_INFINITE,
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0);
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} while (val == 0);
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/* Instruct the MCE to enter system suspend state */
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/* Instruct the MCE to enter system suspend state */
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(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
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TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);
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}
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}
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}
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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@ -25,9 +25,6 @@
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#include <tegra_private.h>
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#include <tegra_private.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
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extern uint64_t tegra_enable_l2_ecc_parity_prot;
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/*******************************************************************************
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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* The Tegra power domain tree has a single system level power domain i.e. a
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* single root node. The first entry in the power domain descriptor specifies
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* single root node. The first entry in the power domain descriptor specifies
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@ -45,6 +42,14 @@ const unsigned char tegra_power_domain_tree_desc[] = {
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PLATFORM_MAX_CPUS_PER_CLUSTER
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PLATFORM_MAX_CPUS_PER_CLUSTER
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};
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};
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/*******************************************************************************
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* This function returns the Tegra default topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return tegra_power_domain_tree_desc;
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}
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/*
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/*
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* Table of regions to map using the MMU.
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* Table of regions to map using the MMU.
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*/
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*/
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@ -137,49 +142,15 @@ uint32_t plat_get_console_from_id(int id)
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return tegra186_uart_addresses[id];
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return tegra186_uart_addresses[id];
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}
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}
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/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */
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#define TEGRA186_VER_A02P 0x1201
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/*******************************************************************************
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/*******************************************************************************
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* Handler for early platform setup
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* Handler for early platform setup
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******************************************************************************/
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******************************************************************************/
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void plat_early_platform_setup(void)
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void plat_early_platform_setup(void)
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{
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{
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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uint32_t chip_subrev, val;
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/* sanity check MCE firmware compatibility */
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/* sanity check MCE firmware compatibility */
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mce_verify_firmware_version();
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mce_verify_firmware_version();
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/*
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* Enable ECC and Parity Protection for Cortex-A57 CPUs
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* for Tegra A02p SKUs
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*/
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if (impl != DENVER_IMPL) {
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/* get the major, minor and sub-version values */
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chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) &
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SUBREVISION_MASK;
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/* prepare chip version number */
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val = (tegra_get_chipid_major() << 12) |
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(tegra_get_chipid_minor() << 8) |
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chip_subrev;
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/* enable L2 ECC for Tegra186 A02P and beyond */
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if (val >= TEGRA186_VER_A02P) {
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val = read_l2ctlr_el1();
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val |= L2_ECC_PARITY_PROTECTION_BIT;
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write_l2ctlr_el1(val);
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/*
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* Set the flag to enable ECC/Parity Protection
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* when we exit System Suspend or Cluster Powerdn
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*/
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tegra_enable_l2_ecc_parity_prot = 1;
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}
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}
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}
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}
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/* Secure IRQs for Tegra186 */
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/* Secure IRQs for Tegra186 */
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@ -51,7 +51,7 @@ int plat_sip_handler(uint32_t smc_fid,
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uint64_t x2,
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uint64_t x2,
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uint64_t x3,
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uint64_t x3,
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uint64_t x4,
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uint64_t x4,
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void *cookie,
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const void *cookie,
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void *handle,
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void *handle,
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uint64_t flags)
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uint64_t flags)
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{
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{
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