Commit Graph

5345 Commits

Author SHA1 Message Date
Andrius Štikonas 5911d0f6f5 Remove HDCP blob. 2022-06-11 20:30:10 +01:00
Andrius Štikonas 5c5cdc75b8 Increase BAUD_RATE to 1500000, so that it matches U-Boot and kernel. 2022-06-11 20:30:10 +01:00
Olivier Deprez 70313d363b Merge changes from topic "ffa_el3_spmc" into integration
* changes:
  feat(fvp): add plat hook for memory transactions
  feat(spmc): enable handling of the NS bit
  feat(spmc): add support for v1.1 FF-A memory data structures
  feat(spmc/mem): prevent duplicated sharing of memory regions
  feat(spmc/mem): support multiple endpoints in memory transactions
  feat(spmc): add support for v1.1 FF-A boot protocol
  feat(plat/fvp): introduce accessor function to obtain datastore
  feat(spmc/mem): add FF-A memory management code
2022-05-19 18:33:03 +02:00
Madhukar Pappireddy be1d3a1a85 Merge changes from topic "gpt-crc" into integration
* changes:
  feat(partition): verify crc while loading gpt header
  build(hikey): platform changes for verifying gpt header crc
  build(agilex): platform changes for verifying gpt header crc
  build(stratix10): platform changes for verifying gpt header crc
  build(stm32mp1): platform changes for verifying gpt header crc
2022-05-19 16:04:39 +02:00
Marc Bonnici a8be4cd057 feat(fvp): add plat hook for memory transactions
Add call to platform hooks upon successful transmission of a
memory transaction request and as part of a memory reclaim request.
This allows for platform specific functionality to be performed
accordingly.

Note the hooks must be placed in the initial share request and final
reclaim to prevent order dependencies with operations that may take
place in the normal world without visibility of the SPMC.

Add a dummy implementation to the FVP platform.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I0c7441a9fdf953c4db0651512e5e2cdbc6656c79
2022-05-19 15:02:47 +01:00
Marc Bonnici 6a0788bc0e feat(plat/fvp): introduce accessor function to obtain datastore
In order to provide the EL3 SPMC a sufficient datastore to
record memory descriptors, a accessor function is used.
This allows for the backing memory to be allocated in a
platform defined manner, to accommodate memory constraints
and desired use cases.

Provide an implementation for the Arm FVP platform to
use a default value of 512KB memory allocated in the
TZC RAM section.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I92bc55ba6e04bdad429eb52f0d2960ceda682804
2022-05-19 10:57:37 +01:00
Madhukar Pappireddy fd36b00f8a Merge changes from topic "xlnx_zynqmp_misra_fix" into integration
* changes:
  fix(zynqmp): resolve misra 8.3 warnings
  fix(zynqmp): resolve misra R8.4 warnings
2022-05-18 22:10:31 +02:00
Rohit Ner e682c723cd build(hikey): platform changes for verifying gpt header crc
This change makes the necessary additions to makefile of
platforms using partition driver.

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: I0d524760bf52e1d9b4a103f556231f20146bd78e
2022-05-18 06:16:37 -07:00
Rohit Ner 7a756a5717 build(agilex): platform changes for verifying gpt header crc
This change makes the necessary additions to makefile of
platforms using partition driver.

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: I1290972c7d2626262d4b6d68b99bb8f2c4b6744c
2022-05-18 06:15:45 -07:00
Rohit Ner 4f53bd29f9 build(stratix10): platform changes for verifying gpt header crc
This change makes the necessary additions to makefile of
platforms using partition driver.

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: Ie26d9e5943453ce54ee8c72c6e44170577e3afc0
2022-05-18 06:12:46 -07:00
Rohit Ner 7da7f1f0b0 build(stm32mp1): platform changes for verifying gpt header crc
This change makes the necessary additions to makefile of
platforms using partition driver.

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: I66f6daaa0deac984b0aa5f2a182385410189ba8a
2022-05-18 06:11:17 -07:00
Manish V Badarkhe 570c71b20a fix(stm32mp1): include assert.h to fix build failure
stm32mp1 platform build failed with the error [1] in the coverity, to
fix it included assert.h file.

Including bl32/sp_min/sp_min.mk
plat/st/stm32mp1/plat_image_load.c: In function
'plat_get_bl_image_load_info':
plat/st/stm32mp1/plat_image_load.c:30:2: error: implicit declaration of
function 'assert' [-Werror=implicit-function-declaration]
   30 |  assert(bl33 != NULL);
      |  ^~~~~~
plat/st/stm32mp1/plat_image_load.c:9:1: note: 'assert' is defined in
header '<assert.h>'; did you forget to '#include <assert.h>'?
    8 | #include <plat/common/platform.h>
  +++ |+#include <assert.h>
    9 |
cc1: all warnings being treated as errors

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I486bd695298798c05008158545668020babb3eca
2022-05-17 16:34:02 +01:00
Venkatesh Yadav Abbarapu 944e7ea94f fix(zynqmp): resolve misra 8.3 warnings
MISRA Violation: MISRA-C:2012 R.8.3
- Declaration uses a different parameter name than the one present in the
definition.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Id0521afd7383df13870710b7dd2894e788896e5e
2022-05-17 09:30:21 +05:30
Madhukar Pappireddy 420c400a89 Merge changes I2fcf13b7,I153ccb43 into integration
* changes:
  feat(n1sdp): add support for nt_fw_config
  feat(n1sdp): enable trusted board boot on n1sdp
2022-05-16 21:59:08 +02:00
Venkatesh Yadav Abbarapu 610eeac894 fix(zynqmp): resolve misra R8.4 warnings
MISRA Violation: MISRA-C:2012 R.8.4
- Function definition does not have a visible prototype.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I50a2c1adf2e099217770ac665f135302f990b162
2022-05-16 17:29:04 +05:30
Madhukar Pappireddy a921da5ed2 Merge changes If2408af3,If485ff27 into integration
* changes:
  feat(versal): add SMCCC call TF_A_PM_REGISTER_SGI
  feat(versal): add support to reset SGI
2022-05-13 18:13:33 +02:00
Olivier Deprez 0dc2b51681 Merge changes from topic "ns/save_fpregs_context" into integration
* changes:
  feat(sgi): enable fpregs context save and restore
  feat(spm_mm): add support to save and restore fp regs
2022-05-13 17:28:58 +02:00
Sandrine Bailleux 6aed554954 Merge changes from topic "rss/mboot-attest" into integration
* changes:
  docs(maintainers): add PSA, MHU, RSS comms code owners
  feat(plat/arm/fvp): enable RSS backend based measured boot
  feat(lib/psa): mock PSA APIs
  feat(drivers/measured_boot): add RSS backend
  feat(drivers/arm/rss): add RSS communication driver
  feat(lib/psa): add initial attestation API
  feat(lib/psa): add measured boot API
  feat(drivers/arm/mhu): add MHU driver
2022-05-13 16:15:35 +02:00
Sieu Mun Tang 0d19eda0dd fix(intel): remove unused printout
This patch is to remove unused printout.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I507210402dcbaf8369209308ae1fcedaccb0292d
2022-05-13 16:46:25 +08:00
Sieu Mun Tang 673afd6f8e fix(intel): fix configuration status based on start request
This patch is to fix configuration status command now returns
the result based on the last config start command made to the
runtime software. The status type can be either:
- NO_REQUEST (default)
- RECONFIGURATION
- BITSTREAM_AUTH

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1ce4b7b4c741d88de88778f8fbed7dfe83a39fbc
2022-05-13 16:46:20 +08:00
Sieu Mun Tang 762c34a85d style(intel): align the sequence in header file
This patch is to align the sequence of function in header file.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9658aef78b06b744c6c14f95b2821daf5dbb0082
2022-05-13 16:46:17 +08:00
Sieu Mun Tang 58690cd629 fix(intel): remove redundant NOC header declarations
This patch is to remove redundant NOC declarations in
system manager header file. The NOC headers are shareable
across both Stratix 10 and Agilex platforms.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I40ff55eb1d8fe280db1d099d5d1a3c2bf4b4b459
2022-05-13 16:46:12 +08:00
Tanmay Shah fcf6f46931 feat(versal): add SMCCC call TF_A_PM_REGISTER_SGI
This call is used to register and reset SGI interrupt.
Before this functionality was performed using IOCTL_REGISTER_SGI
pm_ioctl EEMI call. It's not correct use of PM_IOCTL as it is
not EEMI functionality. Instead this new SMCCC call will be
handled by TF-A specific handler.

Change-Id: If2408af38b889d29a5c584e8eec5f1672eab4fb5
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-05-12 20:29:41 +02:00
Venkatesh Yadav Abbarapu bf70449ba2 feat(versal): add support to reset SGI
Add "reset" parameter in pm_register_sgi() to reset
SGI number. This will be required if OS wants to reset
SGI number to default state. Caller can reset param to
1 to reset SGI in ATF.

Change-Id: If485ff275df884f74eb67671cac7fa953458afe9
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-05-12 20:29:03 +02:00
sahil cf85030efe feat(n1sdp): add support for nt_fw_config
This patch adds support to load nt_fw_config with the information from
plat_info sds structure which is then passed from BL2 to BL33.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I2fcf13b7bf5ab042ef830157fd9cceedbdca617a
2022-05-12 18:51:53 +02:00
sah01 fe2b37f685 feat(n1sdp): enable trusted board boot on n1sdp
Move from RESET_TO_BL31 boot to a TBBR style boot on N1sdp.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I153ccb43a4a013830973c7a183825d62b372c65e
2022-05-12 18:51:32 +02:00
Madhukar Pappireddy 868f9768bb Merge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration
* changes:
  fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
  fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
  fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
  fix(intel): extending to support large file size for AES encryption and decryption
  feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
  feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
  fix(intel): update certificate mask for FPGA Attestation
  feat(intel): update to support maximum response data size
  feat(intel): support ECDSA HASH Verification
  feat(intel): support ECDSA HASH Signing
  feat(intel): support ECDH request
  feat(intel): support ECDSA SHA-2 Data Signature Verification
  feat(intel): support ECDSA SHA-2 Data Signing
  feat(intel): support ECDSA Get Public Key
  feat(intel): support session based SDOS encrypt and decrypt
  feat(intel): support AES Crypt Service
  feat(intel): support HMAC SHA-2 MAC verify request
  feat(intel): support SHA-2 hash digest generation on a blob
  feat(intel): support extended random number generation
  feat(intel): support crypto service key operation
  feat(intel): support crypto service session
  feat(intel): extend attestation service to Agilex family
  fix(intel): flush dcache before sending certificate to mailbox
  fix(intel): introduce a generic response error code
  fix(intel): allow non-secure access to FPGA Crypto Services (FCS)
  feat(intel): single certificate feature enablement
  feat(intel): initial commit for attestation service
  fix(intel): update encryption and decryption command logic
2022-05-12 16:19:15 +02:00
Madhukar Pappireddy 1f0309d498 Merge "fix(zynqmp): define and enable ARM_XLAT_TABLES_LIB_V1" into integration 2022-05-12 16:14:55 +02:00
Nishant Sharma 18fa43f753 feat(sgi): enable fpregs context save and restore
This is required to prevent Nwd context corruption during StMM
execution.

Standalone MM uses OpenSSL for secure boot, which uses FP registers for
floating point calculations.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I6ed11d4fa5d64c3089a24b66fd048a841c480792
2022-05-11 17:18:21 +01:00
Tamas Ban c44e50b725 feat(plat/arm/fvp): enable RSS backend based measured boot
Enable the RSS backend based measured boot feature.
In the absence of RSS the mocked version of PSA APIs
are used. They always return with success and hard-code data.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I7543e9033a7a21f1b836d911d8d9498c6e09b956
2022-05-11 15:47:32 +02:00
Sieu Mun Tang ac097fdf07 fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
This patch is to add flash dcache after return
response in INTEL_SIP_SMC_MBOX_SEND_CMD.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie9451e352f2b7c41ebb44a1f6be9da35f4600fb9
2022-05-11 17:46:00 +08:00
Sieu Mun Tang 70a7e6af95 fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
This patch is to extend to support large file size
for SHA2/HMAC get digest and verifying. The large
file will be split into smaller chunk and send using
initialize, update and finalize staging method.

Signed-off-by: Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1815deeb61287b32c3e77c5ac1b547b79ef12674
2022-05-11 17:45:57 +08:00
Sieu Mun Tang 1d97dd74cd fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
This patch is to extend to support large file size
for SHA-2 ECDSA data signing and signature verifying.
The large file will be split into smaller chunk and
send using initialize, update and finalize staging method.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: If277b2b375a404fe44b0858006c8ba6316a5ce23
2022-05-11 17:45:55 +08:00
Sieu Mun Tang dcb144f1fb fix(intel): extending to support large file size for AES encryption and decryption
This patch is to extend to support large file size
for AES encryption and decryption. The large file
will be split into smaller chunk and send using
initialize, update and finalize staging method.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie2ceaf247e0d7082aad84faf399fbd18d129c36a
2022-05-11 17:45:50 +08:00
Sieu Mun Tang c436707bc6 feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
A separated SMC function ID of mailbox command
is introduced for the new format of SMC protocol.

The new format of SMC procotol will be started
using by Zephyr.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I7996d5054f76c139b5ad55451c373f5669a1017f
2022-05-11 17:45:37 +08:00
Sieu Mun Tang ad47f1422f feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
A separated SMC function ID of non-mailbox command
is introduced for the new format of SMC protocol.

The new format of SMC procotol will be started
using by Zephyr.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I01cff2739364b1bda2ebb9507ddbcef6095f5d29
2022-05-11 17:43:16 +08:00
Boon Khai Ng fe5637f27a fix(intel): update certificate mask for FPGA Attestation
Update the certificate mask to 0xff to cover all certificate
in Agilex family.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id40bc3aa4b3e4f7568a58581bbb03a75b0f20a0b
2022-05-11 16:57:37 +08:00
Sieu Mun Tang b703facaaa feat(intel): update to support maximum response data size
Update to support maximum (4092 bytes) response data size.
And, clean up the intel_smc_service_completed function to
directly write the response data to addr to avoid additional
copy.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I0a230e73c563d22e6999ad3473587b07382dacfe
2022-05-11 16:57:34 +08:00
Sieu Mun Tang 7e25eb8701 feat(intel): support ECDSA HASH Verification
Supporting the command to send digital signature verification
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic86f531bfe7cc7606699f2b064ac677aaf806a76
2022-05-11 16:57:31 +08:00
Sieu Mun Tang 692541051b feat(intel): support ECDSA HASH Signing
Supporting the command to send digital signature signing
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I12cf0f1ceaf07c33a110eae398d3ad82a9b13d38
2022-05-11 16:57:29 +08:00
Sieu Mun Tang 49446866a5 feat(intel): support ECDH request
This command sends the request on generating a share secret on
Diffie-Hellman key exchange.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic7c8470cf036ea8c17bf87401f49936950b3e1d6
2022-05-11 16:57:25 +08:00
Sieu Mun Tang 583050607e feat(intel): support ECDSA SHA-2 Data Signature Verification
This command support ECC based signature verification on a blob.
Supported ECC algorithm are NISP P-256, NISP P-384, Brainpool 256
and Brainpool 384.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I7f43d2a69bbe6693ec1bb90f32b817cf00f9f5ae
2022-05-11 16:57:23 +08:00
Sieu Mun Tang 07912da1b7 feat(intel): support ECDSA SHA-2 Data Signing
This command support ECC based signing on a blob. Supported ECC algorithm
are NISP P-256, NISP P-384, Brainpool 256 and Brainpool 384.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I82f95ddafa6b62f8cd882fce9a3e63e469c85067
2022-05-11 16:57:20 +08:00
Sieu Mun Tang d2fee94afa feat(intel): support ECDSA Get Public Key
To support the ECDSA feature and send the command
as a request to get the public key

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9d7bb5b6ab8ef7d4f3ceb21ff0068baf3175a1ac
2022-05-11 16:57:17 +08:00
Sieu Mun Tang 537ff05257 feat(intel): support session based SDOS encrypt and decrypt
Extends existing Secure Data Object Service (SDOS) encryption and
decryption mailbox command to include session id and context id. The
new format requires an opened crypto service session.

A separated SMC function ID is introduced for the new format and it is
only supported by Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I2627750e8337c1af66217e9cb45981a9e06e7d19
2022-05-11 16:57:13 +08:00
Sieu Mun Tang 6726390eb0 feat(intel): support AES Crypt Service
Enable Support for AES Crypt Service to send request
to encrypt or decrypt a blob. Command will send a memory
location that SDM will read and also memory location that
SDM will write back after encryption or decryption operation.
Response will be sent back after the crypto operation is done,
and data is written back to the destination

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I86ea4ff64dda2fbb1000591e30fa8cb2640ce954
2022-05-11 16:57:11 +08:00
Sieu Mun Tang c05ea29690 feat(intel): support HMAC SHA-2 MAC verify request
This command sends request on checking the integrity and authenticity
of a blob by comparing the calculated MAC with tagged MAC. The
comparison result will be returned in response.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ifefdf67f088d7612d2ec2459d71faf2ec8181222
2022-05-11 16:57:08 +08:00
Sieu Mun Tang 7e8249a2db feat(intel): support SHA-2 hash digest generation on a blob
This command is to request the SHA-2 hash digest on a blob.
If input has a key, the output shall be key-hash digest.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I08cb82d89a8e8f7bfe04f5f01e079ea49fe38cf5
2022-05-11 16:57:02 +08:00
Sieu Mun Tang 24f9dc8a43 feat(intel): support extended random number generation
The random number generation (RNG) mailbox command format
is updated to extends the support to upto 4080 bytes random
number generation. The new RNG format requires an opened
crypto service session.

A separated SMC function ID is introduced for the new RNG
format and it is only supported by Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I3f044a3c01ff7cb50be4705e2c1f982bf6f61432
2022-05-11 16:56:45 +08:00
Sieu Mun Tang 342a0618c7 feat(intel): support crypto service key operation
Support crypto service key operation mailbox commands through SMC.

Crypto service key operation begin by sending an open crypto service
session request to SDM firmware. Once successfully open the session,
send crypto service key management commands (import, export, remove
and get key info) with the associated session id to SDM firmware.
The crypto service key is required before perform any crypto service
(encryption, signing, etc). Last, close the session after finishes
crypto service. All crypto service keys associated with this session
will be erased by SDM firmware.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I02406533f38b9607eb1ec7e1395b9dc2d084a9e3
2022-05-11 10:06:41 +08:00