In extreme cases, the number of secure regions is one more than
non-secure regions. So array "s_base" and "s_top"s size
in struct param_ddr_usage need to be adjust to "DDR_REGION_NR_MAX + 1".
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifc09da2c8f8afa1aebcc78f8fbc21ac95abdece2
Use space after #define consistently, drop useless parenthesis,
no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I72846d8672cab09b128e3118f4b7042a5a9c0df5
This patch changes the destination address of BL31 and BL32 From
fixed address for getting from the each certificates.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream rework
Change-Id: Ide11776feff25e6fdd55ab28503a15b658b2e0d5
* changes:
uniphier: make I/O register region configurable
uniphier: make PSCI related base address configurable
uniphier: make counter control base address configurable
uniphier: make UART base address configurable
uniphier: make pinmon base address configurable
uniphier: make NAND controller base address configurable
uniphier: make eMMC controller base address configurable
The offset there is the virtual address space on the bus side (1-9GB for 8GB RAM),
and that emi_mpu_set_region_protection will translate to the physical memory space (0-8GB).
8GB is 33-bit (the memory bus width is 33-bit on this platform),
so 0x23FFFFFFFUL-EMI_PHY_OFFSET = 0x1_FFFF_FFFF.
Change-Id: I7be4759ed7546f7e15a5868b6f08988928c34075
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
DynamIQ based designs have upto 8 CPUs in each cluster. This
patch fixes the device tree node which describes the topology
of the CPU for DynamIQ FVP Model.
Change-Id: I7146bc79029ce38314026d4853e5b6406863725c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Adding support for generating a semi-random number required for
enabling building TF-A with stack protector support.
TF-A for corstone-700 may now be built using ENABLE_STACK_PROTECTOR=all
Change-Id: I03e1be1a8d4e4a822cf286f3b9ad4da4337ca765
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
* changes:
uniphier: extend boot device detection for future SoCs
uniphier: change block_addressing flag to bool
uniphier: change the return value type of .is_usb_boot() to bool
Pad the .rodata section to 16 bytes as ld.lld does not apply the ALIGN
statement on the .data section to the LMA. Fixes boot failure on builds
where the .rodata section happens to not be 16 bytes aligned.
Change-Id: I4e95678f73d8b326c5fc749dc7d0ce84e2d603f5
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Add SMC_GET_GIC_BASE_GICR option to SMC_FC_GET_REG_BASE and
SMC_FC64_GET_REG_BASE calls for returning the base address of the gic
redistributor added in gic version 3.
Bug: 122357256
Change-Id: Ia7c287040656515bab262588163e0c5fc8f13a21
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Some platforms define GICD_BASE instead of PLAT_ARM_GICD_BASE but the
meaning is the same.
Change-Id: I1bb04bb49fdab055b365b1d70a4d48d2058e49df
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Some platforms define BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE, but
the meaning is the same.
Change-Id: I93d96dca442e653435cae6a165b1955efe2d2b75
Signed-off-by: Arve Hjønnevåg <arve@android.com>
If CC points to clang the linker was set to ld.lld. Copy the diectory
name from CC is it has one.
Change-Id: I50aef5dddee4d2540b12b6d4e68068ad004446f7
Signed-off-by: Arve Hjønnevåg <arve@android.com>
This patch adds information on the PMU configuration registers
and security considerations related to the PMU.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I36b15060b9830a77d3f47f293c0a6dafa3c581fb
The on-chip SRAM region will be changed in the next SoC. Make it
configurable. Also, split the mmap code into a new helper function
so that it can be re-used for another boot mode.
Change-Id: I89f40432bf852a58ebc9be5d9dec4136b8dc010b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The I/O register region will be changed in the next SoC. Make it
configurable.
Change-Id: Iec0cbd1ef2d0703ebc7c3d3082edd73791bbfec9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The next SoC will have:
- No boot swap
- SD boot
- No USB boot
Add new fields to handle this.
Change-Id: I772395f2c5dfc612e575b0cbd0657a5fa9611c25
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The register base address will be changed in the next SoC. Make it
configurable.
Change-Id: Ibe07bd9db128b0f7e629916cb6ae21ba7984eca9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The flag, uniphier_emmc_block_addressing, is boolean logic, so
"bool' is more suitable.
uniphier_emmc_is_over_2gb() is not boolean - it returns 1 / 0
depending on the card density, or a negative value on failure.
Rename it to make it less confusing.
Change-Id: Ia646b1929147b644e0df07c46b54ab80548bc3bd
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The register base will be changed in the next SoC. Make it
configurable.
Change-Id: I4a7cf85fe50e4d71db58a3372a71774e43193bd3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This is boolean logic, so "bool" is more suitable.
Change-Id: I439c5099770600a65b8f58390a4c621c2ee487a5
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The next SoC supports the same UART, but the register base will be
changed. Make it configurable.
Change-Id: Ida5c9151b2f3554afd15555b22838437eef443f7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The register base will be changed in the next SoC. Make it
configurable.
Change-Id: I9fbb6bdd1cf06207618742d4ad7970d911c9bc26
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The next SoC does not support the NAND controller, but make the base
address configurable for consistency and future proof.
Change-Id: I776e43ff2b0408577919b0b72849c3e1e5ce0758
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The next SoC supports the same eMMC controller, but the register
base will be changed. Make it configurable.
Change-Id: I00cb5531bc3d8d49357ad5e922cdd3d785355edf
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Forced hash generation used to always generate hash via RSA encryption.
This patch changes encryption based on ARM_ROTPK_LOCATION.
Also removes setting KEY_ALG based on ARM_ROTPL_LOCATION - there is no
relation between these two.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Id727d2ed06176a243719fd0adfa0cae26c325005
* changes:
SPMD: enable SPM dispatcher support
SPMD: hook SPMD into standard services framework
SPMD: add SPM dispatcher based upon SPCI Beta 0 spec
SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP
SPMD: add support for an example SPM core manifest
SPMD: add SPCI Beta 0 specification header file
This patch adds support to the build system to include support for the SPM
dispatcher when the SPD configuration option is spmd.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: Ic1ae50ecd7403fcbcf1d318abdbd6ebdc642f732
This patch adds support to initialise the SPM dispatcher as a standard
secure service. It also registers a handler for SPCI SMCs exported by
the SPM dispatcher.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I2183adf826d08ff3fee9aee75f021021162b6477
XiaoDong Huang
Marek Vasut
Yoshifumi Hosoya
Chiaki Fujii
Yusuke Goda
Toshiyuki Ogasahara
Mark Dykes
Sandrine Bailleux
Xi Chen
Madhukar Pappireddy
Alexei Fedorov
Morten Borup Petersen
Arve Hjønnevåg
Louis Mayencourt
Petre-Ionut Tudor
Olivier Deprez
joanna.farley
Masahiro Yamada
Max Shvetsov
Manish Pandey
Achin Gupta