Commit Graph

8 Commits

Author SHA1 Message Date
Toshiyuki Ogasahara 042d710d1d feat(plat/rcar3): update DDR setting for R-Car D3
Update R-Car D3 DDR setting rev.0.02.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I3e3a202fbb0ff1f0f38a968ab5f8633604a46432
2021-09-12 01:13:48 +02:00
Toshiyuki Ogasahara 726050b8e2 feat(drivers/rcar3): ddr: add function to judge a DDR rank
This commit adds the function to change the settings used for DDR
initialization depending on the board ID and DDR rank.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I94d550cea620748f5b15499fed1b791a69d61592
2021-07-10 17:35:32 +02:00
Chiaki Fujii ec767c1b99 fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168
2021-07-10 17:35:28 +02:00
Lad Prabhakar 30663f34e7 drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df
2021-04-20 16:17:50 +01:00
Lad Prabhakar b939cbbb8d drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
Add support for initializing DRAM on RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0
2021-04-20 16:17:50 +01:00
Lad Prabhakar fe5929c19d drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
Add support for initializing DRAM on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9
2021-04-20 16:17:49 +01:00
Lad Prabhakar 778db0e924 drivers: renesas: rzg: Switch using common ddr code
Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f
2021-04-20 16:17:49 +01:00
Lad Prabhakar faf5587cfd drivers: renesas: ddr: Move to common
Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I9aef73d3e9a027a127ce7483b72d339559866727
2021-04-20 16:17:49 +01:00