Commit Graph

5359 Commits

Author SHA1 Message Date
Paul Beesley 653279b015 doc: Add minimal Sphinx support
Add the essentials for supporting a Sphinx documentation build:

- A makefile under docs/ to invoke Sphinx with the desired output
  format
- A Sphinx master configuration file (conf.py)
- A single, top-level index page (index.rst)
- The TF.org logo that is integrated in the the sidebar of the
  rendered output

Change-Id: I85e67e939658638337ca7972936a354878083a25
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-05-21 12:31:25 +01:00
Sandrine Bailleux b189a20613 Merge "Fix docs references to header files" into integration 2019-05-21 08:55:31 +00:00
John Tsichritzis ce8dc18773 Fix docs references to header files
Change-Id: I5c06e777d93ac653a853997c2b7c1c9d09b1e49c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-21 09:38:11 +01:00
Sandrine Bailleux af9ae7cfa1 Merge "Update docs for FVP v11.6" into integration 2019-05-21 08:17:16 +00:00
John Tsichritzis 532a67dd16 Update docs for FVP v11.6
Change-Id: I33c1bf49aa10867e1a2ca4c167112b99bf756dda
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-20 14:07:15 +01:00
Soby Mathew 482fc9c888 Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration
* changes:
  N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
  N1SDP: Fix DRAM2 start address
  Add option for defining platform DRAM2 base
  Disable speculative loads only if SSBS is supported
2019-05-16 08:33:56 +00:00
Soby Mathew d8b11091b6 Merge "plat: imx8mq: Remove duplicated linker symbols" into integration 2019-05-15 16:00:40 +00:00
Soby Mathew 519a7db252 Merge "drivers: ufs: Extend the delay after reset to wait for some slower chips" into integration 2019-05-15 15:58:17 +00:00
Soby Mathew eefdb4fb21 Merge "Remove .arch directives from spinlock.S" into integration 2019-05-15 15:54:32 +00:00
Soby Mathew acc18c1fca Merge "SMMUv3: Abort DMA transactions" into integration 2019-05-15 15:54:16 +00:00
Sami Mujawar 603b372e53 N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
N1SDP exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ
can be written but does not reflect the value of the CNTFRQ register
in CNTCTLBase frame. This doesn't follow ARM ARM in that the value
updated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ.

Hence enable the workaround (applied to Juno) for N1SDP that updates
the CNTFRQ register in the Non Secure CNTBaseN frame.

Change-Id: Id89ee1bca0f25c9d62f8f794f2c4f4e618cdf092
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2019-05-15 11:43:20 +01:00
Sami Mujawar 49d64e5d0e N1SDP: Fix DRAM2 start address
The default DRAM2 start address for Arm platforms
is 0x880000000. However, for N1SDP platform this is
0x8080000000.

Fix the DRAM2 start address by initialising
PLAT_ARM_DRAM2_BASE.

Without this fix there is a mismatch of the System
memory region view as seen by the BL31 runtime
firmware (PSCI) versus the view of the OS (which
is based on the description provided by UEFI. In
this case UEFI is correctly describing the DRAM2
start address).

This implicates in secondary cores failing to start
on some Operating Systems if the OS decides to place
the secondary start address in the mismatched region.

Change-Id: I57220e753219353dda429868b4c5e1a69944cc64
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2019-05-15 11:43:19 +01:00
Sami Mujawar 6bb6015f91 Add option for defining platform DRAM2 base
The default DRAM2 base address for Arm platforms
is 0x880000000. However, on some platforms the
firmware may want to move the start address to
a different value.

To support this introduce PLAT_ARM_DRAM2_BASE that
defaults to 0x880000000; but can be overridden by
a platform (e.g. in platform_def.h).

Change-Id: I0d81195e06070bc98f376444b48ada2db1666e28
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2019-05-15 11:42:39 +01:00
Sami Mujawar eca6e45336 Disable speculative loads only if SSBS is supported
Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative
loads (SSBS) is implemented, before disabling speculative
loads.

Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2019-05-14 15:57:10 +01:00
John Stultz cbebadf595 drivers: ufs: Extend the delay after reset to wait for some slower chips
We've seen issues with some THG based UFS chips, where
after reset the LUNs don't always enumerate properly.

After some debugging, we found that extending the mdelay
here seems to resolve the issue by giving the chips enough
time to complete reset.

Change-Id: I848f810b2438ed6ad3d33db614c61d2cef9ac400
Signed-off-by: John Stultz <john.stultz@linaro.org>
2019-05-13 17:11:07 -07:00
Jacky Bai b05631afdc plat: imx8mq: Remove duplicated linker symbols
Remove duplicated linker symbols, resue the symbols
defined in bl_common.h

Change-Id: I10de450eccc78c09b61a8ae7126bf4f4029fa682
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-05-13 21:55:53 +08:00
Alexei Fedorov 02a85c1116 Remove .arch directives from spinlock.S
This patch removes .arch "arm8.1-a" and "armv8-a"
directives which overwrite ASFLAGS_aarch64 option based
on ARM_ARCH_MINOR passed to Makefile and cause
translation errors like
"selected processor does not support `bti jc'"
for armv8.5-a targets when BTI support is enabled.

Change-Id: Idca5b66ed1e5d86e2188b0c0f16c3819990957c4
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-05-13 09:50:27 +01:00
Alexei Fedorov 1461ad9feb SMMUv3: Abort DMA transactions
For security DMA should be blocked at the SMMU by default
unless explicitly enabled for a device. SMMU is disabled
after reset with all streams bypassing the SMMU, and
abortion of all incoming transactions implements a default
deny policy on reset.
This patch also moves "bl1_platform_setup()" function from
arm_bl1_setup.c to FVP platforms' fvp_bl1_setup.c and
fvp_ve_bl1_setup.c files.

Change-Id: Ie0ffedc10219b1b884eb8af625bd4b6753749b1a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-05-10 16:09:19 +01:00
Soby Mathew c33aa45f44 Merge "Initialize platform for MediaTek mt8183" into integration 2019-05-10 10:42:18 +00:00
Antonio Niño Díaz 4c4ec95b81 Merge "maintainers: Step down as sub-maintainer" into integration 2019-05-10 08:57:32 +00:00
Antonio Niño Díaz 18113ba7f5 Merge "plat: imx8m: Implement IMX_SIP_BUILDINFO" into integration 2019-05-10 08:51:29 +00:00
kenny liang 3fa9dec43d Initialize platform for MediaTek mt8183
- Add basic platform setup
- Add generic CPU helper functions
- Add delay timer platform implementation
- Use TI 16550 uart driver

Change-Id: I1c29569c68fe9fca5e10e88a22a29690bab7141f
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
2019-05-10 10:30:17 +08:00
Leonard Crestez 950d05f752 plat: imx8m: Implement IMX_SIP_BUILDINFO
The IMX_SIP_BUILDINFO call was implemented for imx8qm and imx8qx but
it's also applicable to imx8m.

This fixes U-Boot not printing commit hash on 8m with upstream TF-A.

Change-Id: Idcfd9729eaaccf329c24e241da325f1f6cd3c880
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-05-09 17:20:43 +03:00
Antonio Nino Diaz 550bab78f1 maintainers: Step down as sub-maintainer
I'm giving full maintainership of the Raspberry Pi 3 platform port to
Paul. I'm also leaving the GXBB maintainership to Andre, who is also
happy to pass it on to someone else who is more interested in it.

Change-Id: Ieb2212f5fc11ebde9fc0c857e9e305d691d4ee3f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-05-09 14:26:25 +01:00
Antonio Niño Díaz 6079e44743 Merge "Add Makefile check for PAuth and AArch64" into integration 2019-05-09 12:49:37 +00:00
John Tsichritzis dfc66a178b Add Makefile check for PAuth and AArch64
Pointer authentication is supported only in AArch64. A relevant check is
added for that in the Makefile.

Change-Id: I021ba65a9bd5764fd33292bee42617015e04a870
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-09 11:31:14 +01:00
Soby Mathew f2f0846598 Merge "docs: Update contribution guidelines for binary components" into integration 2019-05-08 13:41:56 +00:00
Antonio Niño Díaz d62eae77de Merge changes I286b925e,I1151c2bc into integration
* changes:
  plat: imx8mq: Only keep IRQ 32 unmasked
  plat: imx8mq: gpc: Enable all power domain by default
2019-05-08 13:34:04 +00:00
Soby Mathew ac86469403 Merge "Fix RST rendering and other typos" into integration 2019-05-08 13:06:19 +00:00
John Tsichritzis 6d0512f5c1 Fix RST rendering and other typos
1) One space was missing from the indentation and, hence, rendering error
was generated in the user guide.
2) Partially reword Pointer Authentication related info.

Change-Id: Id5e65d419ec51dd7764f24d1b96b6c9942d63ba4
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-08 14:03:51 +01:00
Leonard Crestez 7696880ad4 plat: imx8mq: Only keep IRQ 32 unmasked
Only IRQ 32 (SPI 0) needs to be kept unmasked, not everything divisible
by 32.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Change-Id: I286b925eead89218cfeddd82f53a634f3447d212
2019-05-08 14:23:07 +03:00
Leonard Crestez e1958506ae plat: imx8mq: gpc: Enable all power domain by default
This is similar to imx8mm and allows uboot to run fastboot over USB otg.

There is a different set of power domains on 8mq but same bits covers
all off them.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Change-Id: I1151c2bc2d32b1e02b4db16285b3d30cabc0d64d
2019-05-08 14:23:02 +03:00
Soby Mathew 0cdbd023e1 Merge changes from topic "sm/fix_a76_errata" into integration
* changes:
  Workaround for cortex-A76 errata 1286807
  Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
2019-05-07 14:31:25 +00:00
Soby Mathew f85edcea5f Workaround for cortex-A76 errata 1286807
The workaround for Cortex-A76 errata #1286807 is implemented
in this patch.

Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-05-07 13:46:47 +01:00
Soby Mathew e6e1d0ac16 Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds are disabled
by default and have to be explicitly enabled by the platform integrator.

Change-Id: I70474927374cb67725f829d159ddde9ac4edc343
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-05-07 13:46:47 +01:00
Soby Mathew 854ca7daf9 Merge "Add compile-time errors for HW_ASSISTED_COHERENCY flag" into integration 2019-05-03 13:35:38 +00:00
John Tsichritzis 076b5f02e2 Add compile-time errors for HW_ASSISTED_COHERENCY flag
This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660

The introduced changes are the following:

1) Some cores implement cache coherency maintenance operation on the
hardware level. For those cores, such as - but not only - the DynamIQ
cores, it is mandatory that TF-A is compiled with the
HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is
unpredictable. To prevent this, compile time checks have been added and
compilation errors are generated, if needed.

2) To enable this change for FVP, a logical separation has been done for
the core libraries. A system cannot contain cores of both groups, i.e.
cores that manage coherency on hardware and cores that don't do it. As
such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the
libraries only of the relevant cores.

3) The neoverse_e1.S file has been added to the FVP sources.

Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-03 14:23:55 +01:00
Soby Mathew b9c1d185bb Merge "SMMUv3: refactor the driver code" into integration 2019-05-03 11:09:02 +00:00
Alexei Fedorov ccd4d475ea SMMUv3: refactor the driver code
This patch is a preparation for the subsequent changes in
SMMUv3 driver. It introduces a new "smmuv3_poll" function
and replaces inline functions for accessing SMMU registers
with mmio read/write operations. Also the infinite loop
for the poll has been replaced with a counter based timeout.

Change-Id: I7a0547beb1509601f253e126b1a7a6ab3b0307e7
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-05-03 09:27:46 +00:00
Soby Mathew 8917380a1e Merge changes from topic "rk3399q7" into integration
* changes:
  rockchip: Disable binary generation for all SoCs.
  build_macros: Add mechanism to prevent bin generation.
2019-05-02 11:25:26 +00:00
Christoph Müllner 33218d2a81 rockchip: Disable binary generation for all SoCs.
All supported Rockchip SoCs (RK3288, RK3328, RK3368 and RK3399)
have non-continuous memory areas in the linker script with a huge
gap between them. This results in extremely padded binary images
with a size of about 4 GiB.

E.g. on the RK3399 we have the following memory areas (and base addresses):
RAM (0x1000), SRAM (0xFF8C0000), and PMUSRAM (0xFF3B0000).

Consumers of the TF-A project (e.g. coreboot or U-Boot) therefore
use the ELF image instead, which has a size of a few hundred kBs.

In order to prevent the generation of a huge and useless file,
this patch disables the binary generation for all affected Rockchip
SoCs.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I4ac65bdf1e598c3e1a59507897d183aee9a36916
2019-05-02 12:27:19 +02:00
Christoph Müllner 9e4609f103 build_macros: Add mechanism to prevent bin generation.
On certain platforms it does not make sense to generate
TF-A binary images. For example a platform could make use of serveral
memory areas, which are non-continuous and the resulting binary
therefore would suffer from the padding-bytes.
Typically these platforms use the ELF image.

This patch introduces a variable DISABLE_BIN_GENERATION, which
can be set to '1' in the platform makefile to prevent the binary
generation.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I62948e88bab685bb055fe6167d9660d14e604462
2019-05-02 12:27:19 +02:00
Antonio Niño Díaz b3c8ac1354 Merge changes from topic "rk3399q7" into integration
* changes:
  rockchip: Allow console device to be set by DTB.
  rockchip: Add params_setup to RK3328.
  rockchip: Streamline and complete UARTn_BASE macros.
2019-05-02 10:13:08 +00:00
Christoph Müllner 220c33a2c5 rockchip: Allow console device to be set by DTB.
Currently the compile-time constant PLAT_RK_UART_BASE defines
which UART is used as console device. E.g. on RK3399 it is set
to UART2. That means, that a single bl31 image can not be used
for two boards, which just differ on the UART console.

This patch addresses this limitation by parsing the "stdout-path"
property from the "chosen" node in the DTB. The expected property
string is expected to have the form "serialN:XXX", with
N being either 0, 1, 2, 3 or 4. When the property is found, it will
be used to override PLAT_RK_UART_BASE.

Tested on RK3399-Q7, with a stdout-path of "serial0:115200n8".

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: Iafe1320e77ab006c121f8d52745d54cef68a48c7
2019-05-01 17:52:53 +02:00
Christoph Müllner f476e63f7a rockchip: Add params_setup to RK3328.
params_setup.c provides the function params_early_setup, which
takes care of parsing ATF parameters (bl31_plat_param array,
fdt or coreboot table). As params_early_setup is defined as weak
symbol in bl31_plat_setup.c, providing a platform-specific
bl31_plat_setup implementation is optional.

This patch adds the rockchip-common params_setup.c to the sources
for RK3328. This streamlines the parameter handling for all supported
rockchip SoCs.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I071c03106114364ad2fc408e49cc791fe5b35925
2019-05-01 17:52:53 +02:00
Christoph Müllner 0957b9b271 rockchip: Streamline and complete UARTn_BASE macros.
In order to set the UART base during bootup in common code of
plat/rockchip, we need to streamline the way the UART base addresses
are defined and add the missing definitions and mappings.

This patch does so by following the pattern UARTn_BASE, which is
already in use on RK3399 and RK3328. The numbering itself is derived
from the upstream Linux DTS files of the individual SoCs.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I341a1996f4ceed5f82a2f6687d4dead9d7cc5c1f
2019-05-01 02:15:43 +02:00
Julius Werner 37b6b8d37f docs: Update contribution guidelines for binary components
This patch updates the contribution guidelines to refer to the new
binary repository.

Change-Id: I898dc58973be91c3f87be53a755269fca2e93174
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-04-30 16:13:04 -07:00
Soby Mathew 9a25f98261 Merge "ti: k3: common: Remove MSMC port definitions" into integration 2019-04-30 16:17:09 +00:00
Soby Mathew 2916284377 Merge changes from topic "lm/stack_protector" into integration
* changes:
  juno: Add security sources for tsp-juno
  Add support for default stack-protector flag
2019-04-30 15:43:21 +00:00
Louis Mayencourt 2a3c645b40 juno: Add security sources for tsp-juno
Security sources are required if stack-protector is enabled.

Change-Id: Ia0071f60cf03d48b200fd1facbe50bd9e2f8f282
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-30 14:42:49 +01:00