Commit Graph

7223 Commits

Author SHA1 Message Date
Olivier Deprez 4c65b4decf doc: add spm and spmd related build options
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I93892dbe76611a7a4b852af3272a0e6271ae037b
2020-03-27 13:54:42 +01:00
Manish Pandey f98f464e2a fconf: notify if fw_config dt is not used
Notify if fw_config dt is either not available or not loaded from fip.

Change-Id: I4dfcbe5032503d97f532a3287c5312c581578b68
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2020-03-27 11:21:03 +00:00
Oliver Swede 4b5793c9a8 plat/arm/board/arm_fpga: Compile with additional CPU libraries
This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.

BL31 behaves differently depending on whether or not the CPUs in the
system use cache coherency, and as a result any CPU libraries that are
compiled together must serve processors that are consistent in this
regard.

This compiles a different set of CPU libraries depending on whether or
not the HW_ASSISTED_COHERENCY is enabled at build-time to indicate the
CPUs support hardware-level support for cache coherency. This build
flag is used in the makefile in the same way as the Arm FVP port.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I18300b4443176b89767015e3688c0f315a91c27e
2020-03-26 20:41:59 +00:00
Oliver Swede 62056e4e8f plat/arm/board/arm_fpga: Enable position-independent execution
This allows the BL31 port to run with position-independent execution
enabled so that it can be ran from any address in the system.
This increases the flexibility of the image, allowing it to be ran from
other locations rather than only its hardcoded absolute address
(currently set to the typical DRAM base of 2GB). This may be useful for
future images that describe system configurations with other memory
layouts (e.g. where SRAM is included).

It does this by setting ENABLE_PIE=1 and changing the absolute
address to 0. The load address of bl31.bin can then be specified by
the -l [load address] argument in the fpga-run command (additionally,
this address is required by any preceding payloads that specify the
start address. For ELF payloads this is usually extracted automatically
by reading the entrypoint address in the header, however bl31.bin is a
different file format so has this additional dependency).

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
2020-03-26 20:41:59 +00:00
Oliver Swede e726c75814 plat/arm/board/arm_fpga: Enable port for alternative cluster configurations
This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.

The BL31 port that is uploaded as a payload to the FPGA with an image
should cater for a wide variety of system configurations. This patch
makes the necessary changes to enable it to function with images whose
cluster configurations may be larger (either by utilizing more
clusters, more CPUs per cluster, more threads in each CPU, or a
combination) than the initial image being used for testing.

As part of this, the hard-coded values that configure the size of the
array describing the topology of the power domain tree are increased
to max. 8 clusters, max. 8 cores per cluster & max 4 threads per core.
This ensures the port works with cluster configurations up to these
sizes. When there are too many entries for the number of available PEs,
e.g. if there is a variable number of CPUs between clusters, then there
will be empty entries in the array. This is permitted and the PSCI
library will still function as expected. While this increases its size,
this shouldn't be an issue in the context of the size of BL31, and is
worth the trade-off for the extra compatibility.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I7d4ae1e20b2e99fdbac428d122a2cf9445394363
2020-03-26 20:41:59 +00:00
Oliver Swede 87762bce84 plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller
This initializes the GIC using the Arm GIC drivers in TF-A.
The initial FPGA image uses a GIC600 implementation, and so that its
power controller is enabled, this platform port calls the corresponding
implementation-specific routines.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I88d5a073eead4b653b1ca73273182cd98a95e4c5
2020-03-26 20:41:58 +00:00
Oliver Swede 2d696d1811 plat/arm/board/arm_fpga: Initialize the System Counter
This sets the frequency of the system counter so that the Delay Timer
driver programs the correct value to CNTCRL. This value depends on
the FPGA image being used, and is 10MHz for the initial test image.
Once configured, the BL31 platform setup sequence then enables the
system counter.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
2020-03-26 20:40:50 +00:00
Oliver Swede 7ee4db6e47 plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images
This adds a basic PSCI implementation allow secondary CPUs to be
released from an initial state and continue through to the warm boot
entrypoint.

Each secondary CPU is kept in a holding pen, whereby it polls the value
representing its hold state, by reading this from an array that acts as
a table for all the PEs. The hold states are initially set to 0 for all
cores to indicate that the executing core should continue polling.
To prevent the secondary CPUs from interfering with the platform's
initialization, they are only updated by the primary CPU once the cold
boot sequence has completed and fpga_pwr_domain_on(mpidr) is called.
The polling target CPU will then read 1 (which indicates that it should
branch to the warm reset entrypoint) and then jump to that address
rather than continue polling.

In addition to the initial polling behaviour of the secondary CPUs
before their warm boot reset sequence, they are also placed in a
low-power wfe() state at the end of each poll; accordingly, the PSCI
fpga_pwr_domain_on(mpidr) function also signals an event to all cores
(after updating the target CPU's hold entry) to wake them from this
state, allowing any secondary CPUs that are still polling to check
their hold state again.
This method is in accordance with both the PSCI and Linux kernel
recommendations, as the lessened overhead reduces the energy
consumption associated with the busy-loop.

The table of hold entries is implemented by a global array as shared SRAM
(which is used by other platforms in similar implementations) is not
available on the FPGA images.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I65cfd1892f8be1dfcb285f0e1e94e7a9870cdf5a
2020-03-26 20:40:48 +00:00
Oliver Swede 5cfe699f2b plat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flow
This makes use of the PRELOADED_BL33_BASE flag to indicate to BL31 that
the BL33 payload (kernel) has already been loaded and resides in memory;
BL31 will then jump to the non-secure address.

For this port the BL33 payload is the Linux kernel, and in accordance
with the pre-kernel setup requirements (as specified in the `Booting
AArch64 Linux' documentation:
https://www.kernel.org/doc/Documentation/arm64/booting.txt),
this change also sets up the primary CPU's registers x0-x3 so they are
the expected values, which includes the address of the DTB at x0.

An external linker script is currently required to combine BL31, the
BL33 payload, and any other software images to create an ELF file that
can be uploaded to the FPGA board along with the bit file. It therefore
has dependencies on the value of PRELOADED_BL33_BASE (kernel base) and
the DTB base (plus any other relevant base addresses used to
distinguish the different ELF sections), both of which are set in this
patch.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: If7ae8ee82d1e09fb05f553f6077ae13680dbf66b
2020-03-26 20:22:33 +00:00
Oliver Swede 536d906abc plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image
This adds the minimal functions and definitions to create a basic
BL31 port for an initial FPGA image, in order for the port to be
uploaded to one the FPGA boards operated by an internal group within
Arm, such that BL31 runs as a payload for an image.

Future changes will enable the port for a wide range of system
configurations running on the FPGA boards to ensure compatibility with
multiple FPGA images.

It is expected that this will replace the FPGA fork of the Linux kernel
bootwrapper by performing similar secure-world initialization and setup
through the use of drivers and other well-established methods, before
passing control to the kernel, which will act as the BL33 payload and
run in EL2NS.

This change introduces a basic, loadable port with the console
initialized by setting the baud rate and base address of the UART as
configured by the Zeus image.

It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
2020-03-26 20:22:30 +00:00
Mark Dykes 8d8d9cf2a6 Merge "FVP: Add BL2 hash calculation in BL1" into integration 2020-03-26 18:17:21 +00:00
Yann Gautier 5813e6edbc stm32mp1: use stm32mp_get_ddr_ns_size() function
Instead of using dt_get_ddr_size() and withdrawing the secure and shared
memory areas, use stm32mp_get_ddr_ns_size() function.

Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-26 18:34:01 +01:00
Yann Gautier 9c52e69fb4 stm32mp1: set XN attribute for some areas in BL2
DTB and BL32 area should not be set as executable in MMU during BL2
execution, hence set those areas as MT_RO_DATA.

Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-26 18:33:58 +01:00
Yann Gautier 84686ba347 stm32mp1: dynamically map DDR later and non-cacheable during its test
A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.

The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.

PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.

BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.

Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-26 18:33:39 +01:00
Yann Gautier e6cc3ccfc2 stm32mp1: add a function to get non-secure DDR size
This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT values fits the default DDR range.
This non-secure memory is available for BL33 and non-secure OS.

Change-Id: I162ae5e990a0f9b6b7d07e539de029f1d61a391b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-26 18:30:31 +01:00
Olivier Deprez 4e1ca00978 Merge "Fix warnings in porting-guide.rst" into integration 2020-03-26 17:12:18 +00:00
Sandrine Bailleux 735e9a0e12 Merge "Tegra194: se: increase max. operation timeout to 1 second" into integration 2020-03-26 17:00:38 +00:00
Manish V Badarkhe 2b06610c9b Fix warnings in porting-guide.rst
Fix below warnings appeared in porting-guide.rst
WARNING: Title underline too short.

Change-Id: Ibc0eba0da72a53a5f9b61c49a8bf7a10b17bc3b8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-03-26 15:24:23 +00:00
Sandrine Bailleux 46d88f9dce Merge changes I250c3aa1,Icf816053 into integration
* changes:
  changelog: introduce SPMD, add secure partition loading and tooling
  changelog: add debugfs functionality
2020-03-26 15:21:20 +00:00
Olivier Deprez 62c170700b changelog: introduce SPMD, add secure partition loading and tooling
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I250c3aa199d4e5efa68aa32bf5a1694835be56b7
2020-03-26 15:24:47 +01:00
Olivier Deprez 22193a3ed8 changelog: add debugfs functionality
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icf8160536c249c754b3dfac6f8f49ca7ad3bb0de
2020-03-26 15:09:30 +01:00
Varun Wadekar 78707ef85d Tegra186: increase memory mapped regions
This patch increases MAX_MMAP_REGIONS to 30 to accommodate the
additional dynamic memory mapped region, during Trusty boot.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I461186a3aff5040f14715b87502fc5f1db3bea6e
2020-03-25 16:19:39 -07:00
Alexei Fedorov 0ab496458b FVP: Add BL2 hash calculation in BL1
This patch provides support for measured boot by adding calculation
of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB.

Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-03-25 16:14:26 +00:00
Mark Dykes d9f405edeb Merge "Fix 'tautological-constant-compare' error" into integration 2020-03-25 15:39:26 +00:00
Manish V Badarkhe 4c4a1327ae Fix 'tautological-constant-compare' error
Fixed below 'tautological-constant-compare' error when building the source
code with latest clang compiler <clang version 11.0.0>.

plat/common/plat_psci_common.c:36:2:
error: converting the result of '<<' to a boolean always evaluates
to true [-Werror,-Wtautological-constant-compare]
        PMF_STORE_ENABLE)
        ^
include/lib/pmf/pmf.h:28:29: note: expanded from macro 'PMF_STORE_ENABLE'
PMF_STORE_ENABLE        (1 << 0)

This error is observed beacuse of CASSERT placed in
"PMF_DEFINE_CAPTURE_TIMESTAMP" which do below stuff:
CASSERT(_flags, select_proper_config);
where _flags = PMF_STORE_ENABLE (1 << 0) which always results true.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifa82ea202496a23fdf1d27ea1798d1f1b583a021
2020-03-25 13:58:55 +00:00
Manish Pandey 7122259d4f Merge "spm: Add spci manifest binding document" into integration 2020-03-24 23:06:53 +00:00
Mark Dykes ce8dfd2884 Merge "fconf: Clean Arm IO" into integration 2020-03-24 18:14:24 +00:00
Mark Dykes bdc84cb52f Merge "plat/sgi: Bump bl1 RW limit" into integration 2020-03-24 18:13:31 +00:00
Mark Dykes 4f19121de1 Merge "corstone700: updating the kernel arguments to support initramfs" into integration 2020-03-24 15:20:42 +00:00
Manish Pandey f89eea4e3e Merge "context: TPIDR_EL2 register not saved/restored" into integration 2020-03-24 11:22:28 +00:00
Abdellatif El Khlifi e515c1ddad corstone700: updating the kernel arguments to support initramfs
In the context of enabling initramfs this change makes
the kernel arguments compatible with the initramfs requirements

Change-Id: Ifa955a5790ae1398fd8ad9ca1c8272f019c121a6
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-03-24 11:12:14 +00:00
Alexei Fedorov 0d5864d91e Merge "spmd: skip loading of secure partitions on pre-v8.4 platforms" into integration 2020-03-24 11:06:08 +00:00
Varun Wadekar 3d1cac96c0 Tegra194: se: increase max. operation timeout to 1 second
This patch increases the maximum timeout value for SE operation
completion to 1 second. This takes care of some corner cases where
an operation might take more time than the previous timeout value
of 100ms.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I0012448ba372a8bb0e156df7dfe49d7de6d21a68
2020-03-23 13:18:13 -07:00
Olivier Deprez c33ff1985e spmd: skip loading of secure partitions on pre-v8.4 platforms
When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1
then there is no need for TF-A to load secure partitions individually.
In this configuration, SPMC handles secure partition loading at
S-EL1/EL0 levels.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I06a0d88a4811274a8c347ce57b56bb5f64e345df
2020-03-23 19:30:48 +00:00
Manish Pandey 92ce719b55 Merge changes from topic "static_analysis" into integration
* changes:
  io: io_stm32image: correct possible NULL pointer dereference
  plat/st: correctly check pwr-regulators node
  nand: stm32_fmc2_nand: correct xor_ecc.val assigned value
  plat/st: correct static analysis tool warning
  raw_nand: correct static analysis tool warning
  spi: stm32_qspi: correct static analysis issues
2020-03-23 17:37:48 +00:00
Yann Gautier 9543389430 io: io_stm32image: correct possible NULL pointer dereference
This issue was found with cppcheck in our downstream code:
[drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]:
 (warning) Either the condition 'buffer!=0U' is redundant or there is
 possible null pointer dereference: local_buffer.

Change-Id: Ieb615b7e485dc93bbeeed4cd8bf845eb84c14ac9
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-23 16:42:37 +01:00
Yann Gautier e9d1e5afbd plat/st: correctly check pwr-regulators node
This warning was issued by cppcheck in our downstream code:
[plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]:
 (warning) Identical condition 'node<0', second condition is always false

The second test has to check variable pwr_regulators_node.

Change-Id: I4a20c4a3ac0ef0639c2df36309d90a61c02b511f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-23 16:42:35 +01:00
Yann Gautier 9fe181c6a6 nand: stm32_fmc2_nand: correct xor_ecc.val assigned value
The variable is wrongly set to 0L, whereas it is an unsigned int, it should
then be 0U.

Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-23 16:42:33 +01:00
Yann Gautier cd4941def3 plat/st: correct static analysis tool warning
Correct the following sparse warnings:
plat/st/common/stm32mp_dt.c:103:5: warning:
 symbol 'fdt_get_node_parent_address_cells' was not declared.
 Should it be static?
plat/st/common/stm32mp_dt.c:123:5: warning:
 symbol 'fdt_get_node_parent_size_cells' was not declared.
 Should it be static?

As those 2 functions are only used by assert(), put them under
ENABLE_ASSERTIONS flag.

Change-Id: Iad721f12128df83a3de3f53e7920a9c1dce64c56
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-23 16:42:28 +01:00
Yann Gautier 498f2936e0 raw_nand: correct static analysis tool warning
Correct the following warning given by sparse tool:
include/drivers/raw_nand.h:158:3: warning:
 symbol '__packed' was not declared. Should it be static?

Change-Id: I03bd9a8aee5cdc5212ce5225be8033f1a6e92bd9
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-23 16:38:41 +01:00
Yann Gautier 9d22d31080 spi: stm32_qspi: correct static analysis issues
Sparse issue:
drivers/st/spi/stm32_qspi.c:445:5:
 warning: symbol 'stm32_qspi_init' was not declared. Should it be static?

Cppcheck issue:
[drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]:
 (style) Variable 'len' is reassigned a value before the old one has been
 used.
[drivers/st/spi/stm32_qspi.c:178]:
 (style) The scope of the variable 'timeout' can be reduced.

Change-Id: I575fb50766355a6717cbd193fc4a80ff1923014c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-03-23 16:38:41 +01:00
Manish Pandey 73d3941658 Merge "allwinner: H6: Fix GPIO and CCU memory map addresses" into integration 2020-03-23 15:35:16 +00:00
Igor Opaniuk 30617cca3f plat: imx: imx8qx: provide debug uart num as build param
1. This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
provided via DT) to set this configuration during compile time via
IMX_DEBUG_UART build flag.

Also for Colibri i.MX8QXP different pinmux configuration is applied
for UART3, FLEXCAN2_RX/TX pads are muxed to ADMA_UART3_RX/TX.

2. Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A35
doesn't make sense (since UART pinmux/clock configuration is applied
for UART only when DEBUG_CONSOLE_A35 is enabled. Check similar commit
for i.MX8QM 98a69dfd4a("plat: imx: imx8qm: apply clk/pinmux
configuration for DEBUG_CONSOLE")).

Usage:
$ make PLAT=imx8qx IMX_DEBUG_UART=3 DEBUG_CONSOLE=1 bl31

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I5d04939b2e8ee1a5f4b2f3c6241977d3c6e91760
2020-03-23 17:24:21 +02:00
Manish Pandey 907c58b2e1 Merge changes from topic "tegra-downstream-03192020" into integration
* changes:
  Tegra194: move cluster and CPU counter to header file.
  Tegra: gicv2: initialize target masks
  spd: tlkd: support new TLK SMCs for RPMB service
  Tegra210: trigger CPU0 hotplug power on using FC
  Tegra: memctrl: cleanup streamid override registers
  Tegra: memctrl_v2: remove support to secure TZSRAM
  Tegra: include platform headers from individual makefiles
  Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro
  Tegra194: SiP function ID to read SMMU_PER registers
  Tegra: memctrl: map video memory as uncached
  Tegra: remove support for USE_COHERENT_MEM
  Tegra: remove circular dependency with common_def.h
  Tegra: include missing stdbool.h
  Tegra: remove support for SEPARATE_CODE_AND_RODATA=0
2020-03-23 15:24:02 +00:00
Louis Mayencourt 79c70ccb4a spm: Add spci manifest binding document
The manifest binding document defines the expected properties and their formats
to represent a partition manifest in device tree.

Change-Id: I5eb250c7b89e0d828e1fcfce32b121e4081879ec
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-03-23 14:22:29 +00:00
Manish Pandey 1625c88180 Merge "plat/arm/sgi: mark remote chip shared ram as non-cacheable" into integration 2020-03-23 12:00:57 +00:00
Manish Pandey 65396234d9 Merge changes I8ca411d5,Ib5f5dd81,I0488e22c into integration
* changes:
  plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE
  plat: imx: imx8qm: provide debug uart num as build param
  plat: imx: imx8_iomux: fix shift-overflow errors
2020-03-23 11:28:28 +00:00
Andre Przywara 5fac0d3228 allwinner: H6: Fix GPIO and CCU memory map addresses
The base address for both the GPIO and the clock unit of the H6 memory map
have been typo-ed. Fix them to match the Linux DT and the manual.

The H6 code use neither of them, so this doesn't change or fix anything
in the real world, but should be corrected anyway.

The issue was found and reported by Github user "armlabs".

Change-Id: Ic6fdfb732ce1cfc54cbb927718035624a06a9e08
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-03-23 11:04:46 +00:00
Varun Wadekar 2a3dd38459 Tegra: fixup GIC init from the 'on_finish' handler
Commit e9e19fb2fe accidentally removed the
GIC init routine required to initialze the distributor on system resume.

This patch fixes this anomaly and initializes the distributor on system
resume.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3fdc694404faa509952f2d90b1f16541165e583e
2020-03-22 11:45:18 -07:00
Anthony Zhou 9aaa8882eb Tegra194: move cluster and CPU counter to header file.
MISRA rules request that the cluster and CPU counter be unsigned
values and have a suffix 'U'. If the define located in the makefile,
this cannot be done.

This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER
macros to tegra_def.h as a result.

Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2020-03-21 19:00:05 -07:00