This patch updates the configuration file for the checkpatch.pl
script to check for the presence of a 'Signed-off-by' line in the
commit message. This is now required by TF contribution process.
Change-Id: I8bcd6d39a5dcd85547244d60c10a7cd2148c404f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
The values of CP15BEN, nTWI & nTWE bits in SCTLR_EL1 are architecturally
unknown if EL3 is AARCH64 whereas they reset to 1 if EL3 is AArch32. This
might be a compatibility break for legacy AArch32 normal world software if
these bits are not set to 1 when EL3 is AArch64. This patch enables the
CP15BEN, nTWI and nTWE bits in the SCTLR_EL1 if the lower non-secure EL is
AArch32. This unifies the SCTLR settings for lower non-secure EL in AArch32
mode for both AArch64 and AArch32 builds of Trusted Firmware.
FixesARM-software/tf-issues#428
Change-Id: I3152d1580e4869c0ea745c5bd9da765f9c254947
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Updated the user guide to clarify building FIP for AArch32.
The instructions were previously specific to building a FIP for AArch64.
Change-Id: I7bd1a6b8e810cfda411f707e04f479006817858e
Signed-off-by: David Cunado <david.cunado@arm.com>
Update the release notes (readme.md) for the ARM Trusted Firmware
v1.3 release.
Change-Id: Ia1f4eb1897e63eeab7d69a593ba0ad91d50043f5
Signed-off-by: Dan Handley <dan.handley@arm.com>
This include provides nothing useful for TF and prevents building
the fiptool using musl libc[0].
[0] https://www.musl-libc.org/
Change-Id: Ied35e16b9ea2b40213433f2a8185dddc59077884
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
In order to quantify the overall time spent in the PSCI software
implementation, an initial collection of PMF instrumentation points
has been added.
Instrumentation has been added to the following code paths:
- Entry to PSCI SMC handler. The timestamp is captured as early
as possible during the runtime exception and stored in memory
before entering the PSCI SMC handler.
- Exit from PSCI SMC handler. The timestamp is captured after
normal return from the PSCI SMC handler or if a low power state
was requested it is captured in the bl31 warm boot path before
return to normal world.
- Entry to low power state. The timestamp is captured before entry
to a low power state which implies either standby or power down.
As these power states are mutually exclusive, only one timestamp
is defined to describe both. It is possible to differentiate between
the two power states using the PSCI STAT interface.
- Exit from low power state. The timestamp is captured after a standby
or power up operation has completed.
To calculate the number of cycles spent running code in Trusted Firmware
one can perform the following calculation:
(exit_psci - enter_psci) - (exit_low_pwr - enter_low_pwr).
The resulting number of cycles can be converted to time given the
frequency of the counter.
Change-Id: Ie3b8f3d16409b6703747093b3a2d5c7429ad0166
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
This patch adds ARM SiP service for use by ARM standard platforms.
This service is added to support the SMC interface for the Performance
measurement framework(PMF).
Change-Id: I26f5712f9ab54f5f721dd4781e35a16f40aacc44
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
The user guide incorrectly claimed that it is possible to load a
bootwrapped kernel over JTAG on Juno in the same manner as an EL3
payload. In the EL3 payload boot flow, some of the platform
initialisations in BL2 are modified. In particular, the TZC settings
are modified to allow unrestricted access to DRAM. This in turn allows
the debugger to access the DRAM and therefore to load the image there.
In the BL33-preloaded boot flow though, BL2 uses the default TZC
programming, which prevent access to most of the DRAM from secure state.
When execution reaches the SPIN_ON_BL1_EXIT loop, the MMU is disabled
and thus DS-5 presumably issues secure access transactions while trying
to load the image, which fails.
One way around it is to stop execution at the end of BL2 instead. At
this point, the MMU is still enabled and the DRAM is mapped as
non-secure memory. Therefore, the debugger is allowed to access this
memory in this context and to sucessfully load the bootwrapped kernel in
DRAM. The user guide is updated to suggest this alternative method.
Co-Authored-By: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Dan Handley <dan.handley@arm.com>
Change-Id: I537ea1c6d2f96edc06bc3f512e770c748bcabe94
This patch adds necessary updates for building and running Trusted
Firmware for AArch32 to user-guide.md. The instructions for running
on both `FVP_Base_AEMv8A-AEMv8A` in AArch32 mode and
`FVP_Base_Cortex-A32x4` models are added. The device tree files for
AArch32 Linux kernel are also added in the `fdts` folder.
Change-Id: I0023b6b03e05f32637cb5765fdeda8c8df2d0d3e
The `fvp-base-gicv3-psci` and `fvp-foundation-gicv3-psci` device tree source
files did not have psci node entries for `system off` and `system reset`.
Also the DTS files included `rtsm_ve-motherboard-no_psci.dtsi` instead of
`rtsm_ve-motherboard.dtsi`. As a result, the Linux kernel failed to invoke
the PSCI_SYSTEM_OFF/RESET API when being shutdown/reset. This patch corrects
this problem and also updates the corresponding DTB files.
This patch also removes `rtsm_ve-motherboard-no_psci.dtsi` and
`fvp-foundation-motherboard-no_psci.dtsi` files as they are no longer used.
Change-Id: I8ba61a1323035f7508cae663bb490ac0e8a64618
As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON
register.
As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the
CRU_CLKSEL_CON offset is 0x100,not 0x80.
Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529
This patch adds the PSCI library integration guide for AArch32 ARMv8-A
systems `psci-lib-integration-guide.md` to the documentation. The
patch also adds appropriate reference to the new document in
the `firmware-design.md` document.
Change-Id: I2d5b5c6b612452371713399702e318e3c73a8ee0
At present the `el3_entrypoint_common` macro uses `memcpy`
function defined in lib/stdlib/mem.c file, to copy data
from ROM to RAM for BL1. Depending on the compiler being
used the stack could potentially be used, in `memcpy`,
for storing the local variables. Since the stack is
initialized much later in `el3_entrypoint_common` it
may result in unknown behaviour.
This patch adds `memcpy4` function definition in assembly so
that it can be used before the stack is initialized and it
also replaces `memcpy` by `memcpy4` in `el3_entrypoint_common`
macro, to copy data from ROM to RAM for BL1.
Change-Id: I3357a0e8095f05f71bbbf0b185585d9499bfd5e0
It is no longer necessary for contributors to send a CLA to ARM
before making contributions. Contributors must instead add a
"Signed-off-by:" line to each commit, which certifies that the
contribution is made under the Developer Certificate of Origin
(DCO).
Update contributing.md to reflect this new policy and add a copy of
the DCO to the repository.
Change-Id: I7ca98bffc3bf57e8bdd51d763c24f13e415a328b
Signed-off-by: Dan Handley <dan.handley@arm.com>
This patch updates the User Guide to recommend the latest version
of some of the software dependencies of ARM Trusted Firmware.
- Upgrade Linaro release: 16.02 -> 16.06
- Upgrade FVPs
- Foundation v8 FVP: 9.5 -> 10.1
- Base FVPs: 7.6 -> 7.7
- Upgrade mbed TLS library: 2.2.0 -> 2.2.1
Note that the latest release of mbed TLS as of today is 2.3.0 but it has
compilations issues with the set of library configuration options that
Trusted Firmware uses. 2.2.1 is the next most recent release known to
build with TF.
This patch also fixes the markdown formatting of a link in the
User Guide.
Change-Id: Ieb7dd336f4d3110fba060afec4ad580ae707a8f1
The Virtualization field in the ID_PFR1 register has only 2
valid values (0 or 1) but it was incorrectly checked against
unrelated value tied to the SPSR register instead.
This patch fixes the detection of virtualization support by
using the valid values in BL1 context management code.
Change-Id: If12592e343770e1da90f0f5fecf0a3376047ac29
This prevents a warning being emitted in the console during FVP
configuration setup when using the Foundation FVP 9.6 onwards.
Change-Id: I685b8bd0dbd0119af4b0cb3f7d708fcc08e99561
This patch moves the invocation of `psci_setup()` from BL31 and SP_MIN
into `std_svc_setup()` as part of ARM Standard Service initialization.
This allows us to consolidate ARM Standard Service initializations which
will be added to in the future. A new function `get_arm_std_svc_args()`
is introduced to get arguments corresponding to each standard service.
This function must be implemented by the EL3 Runtime Firmware and both
SP_MIN and BL31 implement it.
Change-Id: I38e1b644f797fa4089b20574bd4a10f0419de184
This patch introduces a `psci_lib_args_t` structure which must be
passed into `psci_setup()` which is then used to initialize the PSCI
library. The `psci_lib_args_t` is a versioned structure so as to enable
compatibility checks during library initialization. Both BL31 and SP_MIN
are modified to use the new structure.
SP_MIN is also modified to add version string and build message as part
of its cold boot log just like the other BLs in Trusted Firmware.
NOTE: Please be aware that this patch modifies the prototype of
`psci_setup()`, which breaks compatibility with EL3 Runtime Firmware
(excluding BL31 and SP_MIN) integrated with the PSCI Library.
Change-Id: Ic3761db0b790760a7ad664d8a437c72ea5edbcd6
This patch adds ARM Cortex-A32 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base FVP port.
Change-Id: If3697b88678df737c29f79cf3fa1ea2cb6fa565d
This patch adds support in SP_MIN to receive generic and
platform specific arguments from BL2.
The new signature is as following:
void sp_min_early_platform_setup(void *from_bl2,
void *plat_params_from_bl2);
ARM platforms have been modified to use this support.
Note: Platforms may break if using old signature.
Default value for RESET_TO_SP_MIN is changed to 0.
Change-Id: I008d4b09fd3803c7b6231587ebf02a047bdba8d0
This patch uses the `el3_entrypoint_common` macro to initialize
CPU registers, in SP_MIN entrypoint.s file, in both cold and warm
boot path. It also adds conditional compilation, in cold and warm
boot entry path, based on RESET_TO_SP_MIN.
Change-Id: Id493ca840dc7b9e26948dc78ee928e9fdb76b9e4
This patch adds ARM platform changes in BL2 for AArch32 state.
It instantiates a descriptor array for ARM platforms describing
image and entrypoint information for `SCP_BL2`, `BL32` and `BL33`.
It also enables building of BL2 for ARCH=aarch32.
Change-Id: I60dc7a284311eceba401fc789311c50ac746c51e
Sandrine Bailleux
danh-arm
davidcunado-arm
Soby Mathew
dp-arm
Antonio Nino Diaz
Yatharth Kochar
Jeenu Viswambharan
Andreas Färber
Caesar Wang