Commit Graph

5388 Commits

Author SHA1 Message Date
Ambroise Vincent e5be1f95e5 sgm: Fix bl2 sources
The weak version of plat_get_mbedtls_heap() was being used.

Change-Id: I6da331a098dd1af5bb64729d5b914cfb74b8869e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-11 13:48:15 +01:00
Paul Beesley 573b4cd226 doc: Clarify cert_create build when USE_TBBR_DEFS=0
The user guide documentation for the cert_create tool needs to
mention that a platform must have a platform_oid.h header file
in order to successfully build the cert_create tool when
USE_TBBR_DEFS is 0.

Change-Id: I77f86a022d207e88a79c97741be3eafbfa0c86f1
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-04-11 13:43:52 +01:00
Paul Beesley 551631aa58 plat/sgm: Remove redundant platform_oid.h
This file is used when building the cert_create tool without using
the 'standard' set of Arm OID values as defined in the TBBR
specification (see tbbr_oid.h). This configuration is enabled by
setting USE_TBBR_DEFS to 0 during build.

At the moment this will fail because the header file included by
this file was removed in commit bb41eb7a9d ("cert: move
platform_oid.h to include/tools_share for all platforms"). For
the SGM platform this means that there is no current use for
this file.

Change-Id: I3c82983ada62330f1ab6be6d6c0cf489adabae7b
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-04-11 13:43:52 +01:00
Toshiyuki Ogasahara b028f2c5ab rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3
Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: If8918efad0fcbe6f91b66c0c7438406b1d4fb759
2019-04-11 12:57:04 +02:00
Toshiyuki Ogasahara 7704ff9132 rcar_gen3: drivers: Change to restore timer counter value at resume
Changed to save and restore cntpct_el0 using memory mapped
register for generic timer when System Suspend and Resume.

Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
2019-04-11 12:57:03 +02:00
Yoshifumi Hosoya 4983f8b63c rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode
Very rarely, LPDDR4 power consumption may not decrease
In self-refresh mode.

This patch fixes the DBSC4 self-refresh mode sequence.

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Kenji Miyazawa <kenji.miyazawa.xt@renesas.com>
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Change-Id: I838fa0892b1caf1ecd3f04538b3427e7d971ef59
2019-04-11 12:57:02 +02:00
Toshiyuki Ogasahara 285b6cfe3b rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2
Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I239f4d9f58d38515a49fa1a22cece48b59710d15
2019-04-11 12:57:01 +02:00
Chiaki Fujii 4988c4c165 rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
[IPL/DDR]
- Update DDR setting rev.0.35.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7
2019-04-11 12:57:00 +02:00
Yoshifumi Hosoya d8e666a35d rcar_gen3: drivers: qos: change subslot cycle
Subslot cycle from 132 to 126 as default setting.
Subslot cycle from 264 to 252.

 [IPL/QoS]
 - Update H3 Ver.2.0 QoS setting rev.0.21.
 - Update H3 Ver.3.0 QoS setting rev.0.11.
 - Update M3 Ver.1.1 QoS setting rev.0.19.
 - Update M3 Ver.3.0 QoS setting rev.0.02.
 - Update M3N Ver.1.1 QoS setting rev.0.09.

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I52b1bf880163ce03065dc8933d7f193e45cfd9a5
2019-04-11 12:57:00 +02:00
Yusuke Goda 8c7155878c rcar_gen3: drivers: board: Add new board revision for H3ULCB
Board Revision[2:0]
 3'b000 Rev1.0 OB
 3'b001 Rev1.0 CE
 3'b010 Rev2.0	[New]

Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Change-Id: I0f109cddc95eca78aea34c7149e70f14e2f1620b
2019-04-11 12:56:59 +02:00
Toshiyuki Ogasahara 11d15c3e3f rcar_gen3: plat: Change periodic write DQ training option.
Periodic write DQ training available as default.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I649cfe538e4e2c7e19145ce7d1938ce4361b2529
2019-04-11 12:56:56 +02:00
Clément Péron 523ab5be1a plat: allwinner: common: use r_wdog instead of wdog
Some Allwinner H6 has a broken watchdog that doesn't
make the soc reboot.

Use the R_WATCHDOG instead.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Change-Id: Ie95cc30a80ed517b60b30d6bc2e655a1b53f18ba
2019-04-11 01:57:24 +02:00
Wei Yu 7d76df7db2 hikey960: Fix race condition between hotplug and idles
From the hotplug testing on Hikey960, in some case cores fail to become
online in the system. When some cores are hotplugged off, if other
cores in the same cluster enter into CPU idle states at the meantime,
the cluster will be powered off. This introduces the state machine
malfunction in the power controller, thus when hotplug on the core
afterwards, it fails to boot up the core because the power controller
thinks the cluster is powered on.

This patch is to avoid race condition between hotplug and idles by
preventing cluster power off when some of cores in the cluster are
hotplugged off, if all cores in the same cluster are hotplugged off,
the cluster can be powered off.

Change-Id: Ib2feeb093357c70409a3536cb4f9da9b504fdcbe
Signed-off-by: Wei Yu <yuwei3@hisilicon.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
2019-04-10 21:09:46 +08:00
Joel Hutton c554e1ad82 cache_helpers.s:fix mixed tabs and spaces
Change-Id: I8b7c7888d09200410e1a1c11a070c94dd8013ea7
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-10 10:57:58 +01:00
Joel Hutton f999faca06 Add note about erratum 814220 for A7
On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruction before changing cache. The cache cleaning
code happens to already be doing this, so only a comment was added.

Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-10 10:57:58 +01:00
Antonio Niño Díaz a738e1554c Merge "aarch32: Allow compiling with soft-float toolchain" into integration 2019-04-09 12:31:09 +00:00
Antonio Niño Díaz dbf65238f9 Merge "services/spm: Fix service UUID lookup" into integration 2019-04-09 10:50:59 +00:00
Antonio Niño Díaz 72562aab00 Merge "cpus: Fix Cortex-A12 MIDR mask" into integration 2019-04-09 10:50:52 +00:00
Paul Beesley 00e51ca312 services/spm: Fix service UUID lookup
The spm_sp_get_by_uuid() function is used to look up the secure
partition that provides a given service.

Within this function, memcmp() is used to compare the service
UUIDs but it uses the size of the rdsvc->uuid pointer instead of
the size of its content (missing dereference). This means that only
a partial comparison is performed as UUIDs are 128 bits in length and
rdsvc->uuid is a uint32_t typed pointer.

Instead, use the size of the array pointed to by the svc_uuid parameter,
which will be the full 128 bits, for the comparison.

Change-Id: I258fb0cca3bf19f97b8f2a4c133981647cd050e4
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-04-09 11:10:09 +01:00
Antonio Niño Díaz 01e7e0cadc Merge "Add support for Cortex-A76AE CPU" into integration 2019-04-09 09:21:51 +00:00
Joel Hutton 7a246d64d5 Checkpatch: Style fix
Change-Id: I0cb9f0db1ef3491f55c038a10db5a88d37e89697
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-09 09:29:58 +01:00
Antonio Niño Díaz 999adb9493 Merge changes from topic "jh/cotdesc" into integration
* changes:
  Document changes to auth-framework
  cot-desc: optimise memory further
  Reduce memory needed for CoT description
2019-04-08 14:15:33 +00:00
Alexei Fedorov 9ccc5a5733 Add support for Cortex-A76AE CPU
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-04-08 14:48:55 +01:00
Joel Hutton 699475ac5c Document changes to auth-framework
The data structures in the auth-framework were changed by the previous
patch, and need to be updated.

Change-Id: Icfad2ac688d03d32aa93e45f930a375abbc164a9
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-08 14:27:02 +01:00
Joel Hutton 30070427e3 cot-desc: optimise memory further
This changes the auth_img_desc_t struct to have pointers to struct
arrays instead of struct arrays. This saves memory as many of these
were never used, and can be NULL pointers. Note the memory savings are
only when these arrays are not initialised, as it is assumed these
arrays are fixed length. A possible future optimisation could allow for
variable length.

memory diff:
bl1:        bl2:
    text        text
      -12         -12
    bss         bss
      -1463       0
    data        data
      -56         -48
    rodata      rodata
      -5688       -2592
    total       total
      -7419       -2652

Change-Id: I8f9bdedf75048b8867f40c56381e3a6dc6402bcc
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-08 14:24:21 +01:00
Joel Hutton 0b6377d1c6 Reduce memory needed for CoT description
When Trusted Board Boot is enabled, we need to specify the Chain of
Trust (CoT) of the BL1 and BL2 images. A CoT consists of an array
of image descriptors. The authentication module assumes that each
image descriptor in this array is indexed by its unique image
identifier. For example, the Trusted Boot Firmware Certificate has to
be at index [TRUSTED_BOOT_FW_CERT_ID].

Unique image identifiers may not necessarily be consecutive. Also,
a given BL image might not use all image descriptors. For example, BL1
does not need any of the descriptors related to BL31. As a result, the
CoT array might contain holes, which unnecessarily takes up space in
the BL binary.

Using pointers to auth_img_desc_t structs (rather than structs
themselves) means these unused elements only use 1 pointer worth of
space, rather than one struct worth of space. This patch also changes
the code which accesses this array to reflect the change to pointers.

Image descriptors not needed in BL1 or BL2 respectively are also
ifdef'd out in this patch. For example, verifying the BL31 image is
the responsibility of BL2 so BL1 does not need any of the data
structures describing BL31.

memory diff:
bl1:        bl2:
    text        text
      -20         -20
    bss         bss
      -1463       0
    data        data
      -256        -48
    rodata      rodata
      -5240       -1952
    total       total
      -6979       -2020

Change-Id: I163668b174dc2b9bbb183acec817f2126864aaad
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-08 14:21:21 +01:00
Antonio Niño Díaz 05c6693e50 Merge "Fix restoration of PAuth context" into integration 2019-04-08 13:06:32 +00:00
Heiko Stuebner 8785a7cf72 cpus: Fix Cortex-A12 MIDR mask
The Cortex-A12's primary part number is 0xC0D not 0xC0C, so
fix that to make the A12's cpu operations findable.

Change-Id: I4440a039cd57a2fe425fd8a8ec5499ca8e895e31
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-08 12:47:48 +02:00
Jacky Bai 43c733b1f8 plat: imx8m: remove deprecated code include
The 'drivers/console/aarch64/console.S' is not needed,
so remove it from build to fix the build error when
'ERROR_DEPRECATED'set.

Change-Id: Id047a355f82fd33298b7e2b49eff289d28eb5b56
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-04-08 18:21:45 +08:00
Alexei Fedorov 050136d485 Fix restoration of PAuth context
Replace call to pauth_context_save() with pauth_context_restore()
in case of unknown SMC call.

Change-Id: Ib863d979faa7831052b33e8ac73913e2f661f9a0
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-04-05 13:51:08 +01:00
Grzegorz Jaszczyk f7cdf872f8 plat: marvell: do not rely on argument passed via smc
There is no need to rely on x1 argument.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Change-Id: Ie7766e801e724801b42b66331ba252ede5744a2c
2019-04-05 12:48:43 +02:00
Grzegorz Jaszczyk b143fa7491 plat: marvell: sip: make sure that comphy init will use correct address
The argument passed via x1 is used as a base address for comphy related
routines. Nevertheless validation of this address wasn't good enough and
allowed some non comphy related addresses to slip over.

To overcome this issue make sure that the address passed via SMC points
to valid CP range and allow to proceed comphy initializations only with
correct comphy offset.

This could be fixed in a different way e.g. by passing CP id from the
caller, but since this API is already used with various Linux, U-Boot
and UEFI versions it can't be changed.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Change-Id: Ia74dbc36efcfbefc4a102d31191e6af5808c4a82
2019-04-05 12:48:40 +02:00
Manish Pandey fbd8f6c841 aarch32: Allow compiling with soft-float toolchain
ARMv7 and Cortex-A32(ARMv8/aarch32) uses "arm-linux-gnueabi" toolchain which
has both soft-float and hard-float variants and so there could be scenarios
where soft-float toolchain is used.Even though TF-A documentation recommends
to use hard-float toolchain for aarch32 but there are external projects where
we cannot mandate the selection of toolchain and for those projects at least
the build should not fail.

Current TF-A source fails to build with soft-float toolchain because assembler
does not recognizes "vmsr" instruction which is required to enable floating
point unit.

To avoid this piece of code being compiled with soft-float toolchain add
predefined macro guard " __SOFTFP__" exposed by soft-float toolchain.

Change-Id: I76ba40906a8d622dcd476dd36ab4d277a925996c
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2019-04-05 11:37:19 +01:00
Paul Beesley c48991e1fe doc: Fix heading levels for changelog
The change-log.rst file does not use the same symbols
as the other documents when organising its headings,
sub-headings and so on. In order to compile these
documents together with Sphinx, forming a top-level
index and a consistent structure, it is necessary to
normalise these.

Change-Id: Ib4620ff03a9e76fec9e36e95549016c7b3fe12bb
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-04-05 10:28:36 +01:00
Antonio Niño Díaz 8a08e27232
Merge pull request #1920 from ambroise-arm/av/deprecated
Remove deprecated interfaces
2019-04-04 09:29:22 +01:00
Ambroise Vincent 6e756f6d6d Makefile: remove extra include paths in INCLUDES
Now it is needed to use the full path of the common header files.

Commit 09d40e0e08 ("Sanitise includes across codebase") provides more
information.

Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-03 15:30:46 +01:00
Ambroise Vincent c6cafcd770 Remove deprecated interfaces
Change-Id: I14fcabbdfd53153d1d5f187f6f8b23a045794408
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-03 14:55:18 +01:00
Ambroise Vincent cc69cfd28c tzc: remove deprecated types
Types tzc_action_t and tzc_region_attributes_t are deprecated.

Change-Id: Ieefeb8521a0e1130f39d09b5c0d2728f05084773
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-03 14:55:18 +01:00
Ambroise Vincent be3991c0c3 Console: remove deprecated finish_console_register
The old version of the macro is deprecated.

Commit cc5859ca19 ("Multi-console: Deprecate the
`finish_console_register` macro") provides more details.

Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-03 14:55:18 +01:00
Ambroise Vincent 2cc9777170 Remove deprecated plat_crash_console_*
The default implementations are defined in crash_console_helpers.S. The
platforms have to define plat_crash_console_*.

Implemented placeholders for platforms that were missing helpers.

Change-Id: Iea60b6f851956916e421dfd8c34a62d96eb9148e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-03 14:55:18 +01:00
Antonio Niño Díaz 682c307d2c
Merge pull request #1917 from marex/arm/master/v3meagle-v2.0.1
rcar_gen3: plat: Add R-Car V3M support
2019-04-03 14:06:21 +01:00
Antonio Niño Díaz fc3e159134
Merge pull request #1916 from antonio-nino-diaz-arm/an/spm-xlat
SPM: Some improvements to xlat handling code
2019-04-03 11:20:47 +01:00
Antonio Niño Díaz 18d4d113ec
Merge pull request #1918 from lmayencourt/lm/contrib_guidelines
doc: Update contribution guidelines
2019-04-03 11:20:38 +01:00
Antonio Niño Díaz 1348b6d137
Merge pull request #1915 from repk/gxl
Add support for Amlogic s905x (GXL)
2019-04-03 11:20:21 +01:00
Antonio Nino Diaz 75f364b3e0 SPM: Adjust size of virtual address space per partition
Rather than using a fixed virtual address space size, read all regions
in the resource description of each partition and restrict the virtual
address space size to the one the partition actually needs.

This also allows SPM to take advantage of the extension ARMv8.4-TTST if
the virtual address space size is small enough.

Change-Id: I8646aa95e659136b58b44b040364cdee631f7e82
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-04-03 10:51:31 +01:00
Antonio Nino Diaz 014df18b8e SPM: Refactor xlat context creation
Right now the virtual address space is fixed to
PLAT_VIRT_ADDR_SPACE_SIZE, so all base translation tables are the same
size and need the same alignment. The current code allocates the exact
space needed by this initial table.

However, a following patch is going to allow each partition to choose
the size of its address space based on the memory regions defined in
their resource description, so it isn't possible to determine this at
build time. As this optimization no longer applies, it has to be
removed.

Change-Id: Ia8d19f4981e1017e4ffe0ba136de73d701044cb0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-04-03 10:51:31 +01:00
Antonio Nino Diaz 6de6965b2f SPM: Move shim layer to TTBR1_EL1
This gives each Secure Partition complete freedom on its address space.
Previously, the memory used by the exception vectors was reserved and
couldn't be used. Also, it always had to be mapped, forcing SPM to
generate translation tables that included the exception vectors as well
as the Partition memory regions. With this change, partitions can reduce
their address space size easily.

Change-Id: I67fb5e9bdf2870b73347f23bff702fab0a8f8711
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-04-03 10:51:31 +01:00
Louis Mayencourt 63fdda2d98 doc: Update contribution guidelines
Update the documentation for trustedfirmware.org migration

Change-Id: Ibb7052b0becbec3326164f1503806ca2c2fd4dcc
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-02 16:19:11 +01:00
Remi Pommarel 9b5a8aa58d plat: gxl: Add documentation on building GXL image
Also adds a maintainer for GXL.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
2019-04-02 16:33:59 +02:00
Remi Pommarel 9f52e88636 meson/gxl: Add tool to create bl31 bootable images
GXL platforms need to have a specific header at the beginning of bl31
image to be able to boot. This adds a tool to create that and calls it at
build time.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
2019-04-02 16:33:59 +02:00