Commit Graph

3432 Commits

Author SHA1 Message Date
Louis Mayencourt a6de824f7e fconf: Clean Arm IO
Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This
removes the duplicate io_policies and functions definition.

This patch:
- replace arm_io_storage.c with the content of arm_fconf_io_storage.c
- rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB.
- use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb.
- propagate DEFINES when parsing dts.
- use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb.
- set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior
  of fvp stays the same as it was before the introduction of fconf.

Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-03-16 11:49:19 +00:00
Louis Mayencourt 2fc18a25f5 plat/sgi: Bump bl1 RW limit
Increase bl1 RW limit to allow future development.

Change-Id: I3159b36dbaca798b4c4374c1415cd033d6586388
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-03-13 10:40:57 +00:00
Sandrine Bailleux 4c9ad0df66 Merge "juno/sgm: Maximize space allocated to SCP_BL2" into integration 2020-03-13 08:06:04 +00:00
Mark Dykes d2737fe1c6 Merge changes from topic "mp/enhanced_pal_hw" into integration
* changes:
  plat/arm/fvp: populate pwr domain descriptor dynamically
  fconf: Extract topology node properties from HW_CONFIG dtb
  fconf: necessary modifications to support fconf in BL31 & SP_MIN
  fconf: enhancements to firmware configuration framework
2020-03-12 15:54:28 +00:00
Chris Kay ddc93cbaa4 juno/sgm: Maximize space allocated to SCP_BL2
To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its current (mostly) arbitrary address to the beginning
of the non-shared trusted SRAM.

Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434
Signed-off-by: Chris Kay <chris.kay@arm.com>
2020-03-12 15:12:23 +00:00
Manish Pandey ec2f82ecbf Merge "n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag" into integration 2020-03-12 10:09:31 +00:00
Madhukar Pappireddy 6138ffbc12 plat/arm/fvp: populate pwr domain descriptor dynamically
The motivation behind this patch and following patches is to extract
information about the platform in runtime rather than depending on
compile time macros such as FVP_CLUSTER_COUNT. This partially enables
us to use a single binary for a family of platforms which all have
similar hardware capabilities but differ in configurations.

we populate the data structure describing the power domain hierarchy
of the platform dynamically by querying the number of clusters and cpus
using fconf getter APIs. Compile time macro such as FVP_CLUSTER_COUNT
is still needed as it determines the size of related data structures.

Note that the cpu-map node in HW_CONFIG dts represents a logical
hierarchy of power domains of CPU. However, in reality, the power
domains may not have been physically built in such hierarchy.

Change-Id: Ibcbb5ca7b2c969f8ad03ab2eab289725245af7a9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-03-11 19:27:02 -05:00
Kalyani Chidambaram b8dbf07374 Tegra210: Remove "unsupported func ID" error msg
The platform sip is reporting a "unsupported function ID" if the
smc function id is not pmc command. When actually the smc function id
could be specific to the tegra sip handler.
This patch removes the error reported.

Change-Id: Ia3c8545d345746c5eea6d75b9e6957ca23ae9ca3
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
2020-03-11 13:40:07 -07:00
Varun Wadekar f8827c60c7 Tegra210: support for secure physical timer
This patch enables on-chip timer1 interrupts for Tegra210 platforms.

Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-11 13:40:07 -07:00
Varun Wadekar 91dd7edd31 Tegra: smmu: export handlers to read/write SMMU registers
This patch exports the SMMU register read/write handlers for platforms.

Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-11 13:37:26 -07:00
Pritesh Raithatha a391d4942a Tegra: smmu: remove context save sequence
SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
2020-03-11 13:37:26 -07:00
Varun Wadekar e904448006 Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194
This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.

Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-11 13:37:26 -07:00
Pritesh Raithatha de3fd9b3bb Tegra194: memctrl: lock some more MC SID security configs
The platform code already contains the initial set of MC SID
security configs to be locked during boot. This patch adds some
more configs to the list. Since the reset value of these registers
is already as per expectations, there is no need to change it.

MC SID security configs
- PTCR,
- MIU6R, MIU6W, MIU7R, MIU7W,
- MPCORER, MPCOREW,
- NVDEC1SRD, NVDEC1SRD1, NVDEC1SWR.

Change-Id: Ia9a1f6a6b6d34fb2787298651f7a4792a40b88ab
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
2020-03-11 13:37:26 -07:00
Jeetesh Burman 029dd14e72 Tegra194: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store to PMC scratch registers.

Change-Id: I04cc0eb7f54c69d64b6c34fc2ff62e4cfbdd43b2
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
2020-03-11 13:37:25 -07:00
Jeetesh Burman 2ac7b22387 Tegra194: store TZDRAM base/size to scratch registers
This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: I2f5fd11c87804d20e2698de33be977991c9f6f33
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
2020-03-11 13:31:12 -07:00
kalyani chidambaram 6dbe1c8f4d Tegra194: fix warnings for extra parentheses
armclang displays warnings for extra parentheses, leading to
build failures as warnings are treated as errors.
This patch removes the extra parentheses to fix this issue.

Change-Id: Id2fd6a3086590436eecabc55502f40752a018131
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
2020-03-11 13:31:12 -07:00
Madhukar Pappireddy 4682461ded fconf: Extract topology node properties from HW_CONFIG dtb
Create, register( and implicitly invoke) fconf_populate_topology()
function which extracts the topology related properties from dtb into
the newly created fconf based configuration structure 'soc_topology'.
Appropriate libfdt APIs are added to jmptbl.i file for use with USE_ROMLIB
build feature.

A new property which describes the power domain levels is added to the
HW_CONFIG device tree source files.

This patch also fixes a minor bug in the common device tree file
fvp-base-gicv3-psci-dynamiq-common.dtsi
As this file includes fvp-base-gicv3-psci-common.dtsi, it is necessary
to delete all previous cluster node definitons because DynamIQ based
models have upto 8 CPUs in each cluster. If not deleted, the final dts
would have an inaccurate description of SoC topology, i.e., cluster0
with 8 or more core nodes and cluster1 with 4 core nodes.

Change-Id: I9eb406da3ba4732008a66c01afec7c9fa8ef59bf
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-03-11 11:25:10 -05:00
Madhukar Pappireddy 26d1e0c330 fconf: necessary modifications to support fconf in BL31 & SP_MIN
Necessary infrastructure added to integrate fconf framework in BL31 & SP_MIN.
Created few populator() functions which parse HW_CONFIG device tree
and registered them with fconf framework. Many of the changes are
only applicable for fvp platform.

This patch:
1. Adds necessary symbols and sections in BL31, SP_MIN linker script
2. Adds necessary memory map entry for translation in BL31, SP_MIN
3. Creates an abstraction layer for hardware configuration based on
   fconf framework
4. Adds necessary changes to build flow (makefiles)
5. Minimal callback to read hw_config dtb for capturing properties
   related to GIC(interrupt-controller node)
6. updates the fconf documentation

Change-Id: Ib6292071f674ef093962b9e8ba0d322b7bf919af
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-03-11 11:24:55 -05:00
Mark Dykes f9ea3a6291 Merge "Fix crash dump for lower EL" into integration 2020-03-11 15:39:32 +00:00
Mark Dykes 6654d17e1a Merge "TF-A GICv3 driver: Separate GICD and GICR accessor functions" into integration 2020-03-11 15:38:45 +00:00
Madhukar Pappireddy 25d740c45e fconf: enhancements to firmware configuration framework
A populate() function essentially captures the value of a property,
defined by a platform, into a fconf related c structure. Such a
callback is usually platform specific and is associated to a specific
configuration source.
For example, a populate() function which captures the hardware topology
of the platform can only parse HW_CONFIG DTB. Hence each populator
function must be registered with a specific 'config_type' identifier.
It broadly represents a logical grouping of configuration properties
which is usually a device tree source file.

Example:
> TB_FW: properties related to trusted firmware such as IO policies,
	 base address of other DTBs, mbedtls heap info etc.
> HW_CONFIG: properties related to hardware configuration of the SoC
	 such as topology, GIC controller, PSCI hooks, CPU ID etc.

This patch modifies FCONF_REGISTER_POPULATOR macro and fconf_populate()
to register and invoke the appropriate callbacks selectively based on
configuration type.

Change-Id: I6f63b1fd7a8729c6c9137d5b63270af1857bb44a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-03-11 10:19:21 -05:00
Chandni Cherukuri 303b6d069a n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag
Since N1SDP has a system level cache which is an
external LLC enable the NEOVERSE_N1_EXTERNAL_LLC flag.

Change-Id: Idb34274e61e7fd9db5485862a0caa497f3e290c7
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2020-03-11 16:01:46 +05:30
Sandrine Bailleux 1d4fb1e71d Merge changes from topic "stm32mp1-multi-image" into integration
* changes:
  stm32mp1: platform.mk: support generating multiple images in one build
  stm32mp1: platform.mk: migrate to implicit rules
  stm32mp1: platform.mk: derive map file name from target name
  stm32mp1: platform.mk: generate linker script with fixed name
  stm32mp1: platform.mk: use PHONY for the appropriate targets
2020-03-11 10:03:17 +00:00
Sandrine Bailleux 579c125644 Merge "plat: imx8mm: provide uart base as build option" into integration 2020-03-11 09:37:19 +00:00
Sandrine Bailleux 2f006b2c66 Merge "hikey960: Enable system power off callback" into integration 2020-03-11 09:34:12 +00:00
Sandrine Bailleux f56081e360 Merge changes from topic "xlat" into integration
* changes:
  Factor xlat_table sections in linker scripts out into a header file
  xlat_tables_v2: use ARRAY_SIZE in REGISTER_XLAT_CONTEXT_FULL_SPEC
  xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}
2020-03-11 09:08:04 +00:00
Olivier Deprez 2fd18f03ca Merge "plat/arm: Retrieve the right ROTPK when using the dualroot CoT" into integration 2020-03-11 08:22:47 +00:00
Masahiro Yamada 665e71b8ea Factor xlat_table sections in linker scripts out into a header file
TF-A has so many linker scripts, at least one linker script for each BL
image, and some platforms have their own ones. They duplicate quite
similar code (and comments).

When we add some changes to linker scripts, we end up with touching
so many files. This is not nice in the maintainability perspective.

When you look at Linux kernel, the common code is macrofied in
include/asm-generic/vmlinux.lds.h, which is included from each arch
linker script, arch/*/kernel/vmlinux.lds.S

TF-A can follow this approach. Let's factor out the common code into
include/common/bl_common.ld.h

As a start point, this commit factors out the xlat_table section.

Change-Id: Ifa369e9b48e8e12702535d721cc2a16d12397895
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-11 11:31:46 +09:00
Mark Dykes f09852c97b Merge changes from topic "sb/dualroot" into integration
* changes:
  plat/arm: Pass cookie argument down to arm_get_rotpk_info()
  plat/arm: Add support for dualroot CoT
  plat/arm: Provide some PROTK files for development
2020-03-10 18:34:56 +00:00
Alexei Fedorov 6e19bd563d TF-A GICv3 driver: Separate GICD and GICR accessor functions
This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3.1 and GICv4 support.
NOTE: Platforms need to modify to include both
'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the
single helper file previously.

Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-03-10 09:40:19 +00:00
Varun Wadekar 7d74487c2a Tegra186: store TZDRAM base/size to scratch registers
This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: Ic70914cb958249f06cb58025a24d13734a85e16e
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-09 15:25:16 -07:00
Jeetesh Burman 4eed9c8480 Tegra186: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.

Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
2020-03-09 15:25:16 -07:00
Jeetesh Burman 3827aa8ad2 Tegra186: add support for bpmp_ipc driver
This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
2020-03-09 15:25:16 -07:00
Mithun Maragiri be85f0f7f7 Tegra210: disable ERRATA_A57_829520
ERRATA_A57_829520 disables "indirect branch prediction" for
EL1 on cpu reset, leading to 15% drop in CPU performance
with coremark benchmarks.

Tegra210 already has a hardware fix for ARM BUG#829520,so
this errata is not needed.

This patch disables the errata to get increased performance
numbers.

Change-Id: I0b42e8badd19a8101f6a55d80eb2d953597d3c20
Signed-off-by: Mithun Maragiri <mmaragiri@nvidia.com>
2020-03-09 15:25:15 -07:00
Pravin a69a30ff23 Tegra194: memctrl: add support for MIU4 and MIU5
This patch adds support for memqual miu 4,5.

The MEMQUAL engine has miu0 to miu7 in which miu6 and
miu7 is hardwired to bypass SMMU. So only miu0 to miu5
support is provided.

Change-Id: Ib350334eec521e65f395f1c3205e2cdaf464ebea
Signed-off-by: Pravin <pt@nvidia.com>
2020-03-09 15:25:15 -07:00
Stefan Kristiansson 4b74f6d24c Tegra194: memctrl: remove support to reconfigure MSS
As bpmp-fw is running at the same time as ATF, and
the mss client reconfiguration sequence involves performing
a hot flush resets on bpmp, there is a chance that bpmp-fw is
trying to perform accesses while the hot flush is active.

Therefore, the mss client reconfigure has been moved to
System Suspend resume fw and bootloader, and it can be
removed from here.

Change-Id: I34019ad12abea9681f5e180af6bc86f2c4c6fc74
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
2020-03-09 15:25:15 -07:00
Varun Wadekar f617868678 Tegra: fiq_glue: remove bakery locks from interrupt handler
This patch removes usage of bakery_locks from the FIQ handler, as it
creates unnecessary dependency whenever the watchdog timer interrupt
fires. All operations inside the interrupt handler are 'reads', so
no need for serialization.

Change-Id: I3f675e610e4dabc5b1435fdd24bc28e424f5a8e4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-09 15:25:15 -07:00
Harvey Hsieh 41554fb2eb Tegra210: SE: add context save support
Tegra210B01 SoCs support atomic context save for the two SE
hardware engines. Tegra210 SoCs have support for only one SE
engine and support a software based save/restore mechanism
instead.

This patch updates the SE driver to make this change.

Change-Id: Ia5e5ed75d0fe011f17809684bbc2ed2338925946
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
2020-03-09 15:25:15 -07:00
kalyani chidambaram 24902fae24 Tegra210: update the PMC blacklisted registers
Update the list to include PMC registers that the NS world cannot
access even with smc calls.

Change-Id: I588179b56ebc0c29200b55e6d61535fd3a7a3b7e
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
2020-03-09 15:25:15 -07:00
Varun Wadekar b1481cff46 Tegra: disable CPUACTLR access from lower exception levels
This patch resets the macros to update the CPUACTLR_ELx to make
them generic for all exception levels.

Change-Id: I33e9b860efb543934b654a2f5d775135df7f1aa6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-09 15:25:15 -07:00
Sandrine Bailleux 091576e7f1 Merge changes from topic "tbbr/fw_enc" into integration
* changes:
  docs: qemu: Add instructions to boot using FIP image
  docs: Update docs with firmware encryption feature
  qemu: Support optional encryption of BL31 and BL32 images
  qemu: Update flash address map to keep FIP in secure FLASH0
  Makefile: Add support to optionally encrypt BL31 and BL32
  tools: Add firmware authenticated encryption tool
  TBB: Add an IO abstraction layer to load encrypted firmwares
  drivers: crypto: Add authenticated decryption framework
2020-03-09 15:23:22 +00:00
Sandrine Bailleux a1463c8e67 Merge "uniphier: shrink UNIPHIER_ROM_REGION_SIZE" into integration 2020-03-09 09:25:11 +00:00
Alexei Fedorov b4292bc65e Fix crash dump for lower EL
This patch provides a fix for incorrect crash dump data for
lower EL when TF-A is built with HANDLE_EA_EL3_FIRST=1 option
which enables routing of External Aborts and SErrors to EL3.

Change-Id: I9d5e6775e6aad21db5b78362da6c3a3d897df977
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-03-06 14:17:35 +00:00
Masahiro Yamada 548654bc03 uniphier: shrink UNIPHIER_ROM_REGION_SIZE
Currently, the ROM region is needlessly too large.

The on-chip SRAM region of the next SoC will start from 0x04000000,
and this will cause the region overlap.

Mapping 0x04000000 for the ROM is enough.

Change-Id: I85ce0bb1120ebff2e3bc7fd13dc0fd15dfff5ff6
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-06 20:13:40 +09:00
Sumit Garg 518577627e qemu: Support optional encryption of BL31 and BL32 images
Enable encryption IO layer to be stacked above FIP IO layer for optional
encryption of Bl31 and BL32 images in case ENCRYPT_BL31 or ENCRYPT_BL32
build flag is set.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I24cba64728861e833abffc3d5d9807599c49feb6
2020-03-06 16:40:37 +05:30
Sumit Garg a886bbeceb qemu: Update flash address map to keep FIP in secure FLASH0
Secure FLASH0 memory map looks like:
- Offset: 0 to 256K -> bl1.bin
- Offset: 256K to 4.25M -> fip.bin

FLASH1 is normally used via UEFI/edk2 to keep varstore.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I6883f556c22d6a5d3fa3846c703bebc2abe36765
2020-03-06 16:40:37 +05:30
Sumit Garg 2be57b8658 TBB: Add an IO abstraction layer to load encrypted firmwares
TBBR spec advocates for optional encryption of firmwares (see optional
requirement: R060_TBBR_FUNCTION). So add an IO abstaction layer to
support firmware decryption that can be stacked above any underlying IO/
packaging layer like FIP etc. It aims to provide a framework to load any
encrypted IO payload.

Also, add plat_get_enc_key_info() to be implemented in a platform
specific manner as handling of encryption key may vary from one platform
to another.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I9892e0ddf00ebecb8981301dbfa41ea23e078b03
2020-03-06 16:40:37 +05:30
Olivier Deprez d95f7a7287 Merge changes from topic "spmd-sel2" into integration
* changes:
  SPMD: add command line parameter to run SPM at S-EL2 or S-EL1
  SPMD: smc handler qualify secure origin using booleans
  SPMD: SPMC init, SMC handler cosmetic changes
  SPMD: [tegra] rename el1_sys_regs structure to sys_regs
  SPMD: Adds partially supported EL2 registers.
  SPMD: save/restore EL2 system registers.
2020-03-06 08:18:03 +00:00
Manish Pandey ac56d00838 Merge changes from topic "console_t_drvdata_fix" into integration
* changes:
  imx: console: Use CONSOLE_T_BASE for UART base address
  Tegra: spe: use CONSOLE_T_BASE to save MMIO base address
2020-03-05 22:45:12 +00:00
Igor Opaniuk 60a23af2e5 plat: imx8mm: provide uart base as build option
Some boards (f.e. Verdin i.MX8M Mini) use different UART base address
for serial debug output, so make this value configurable (as a
build option).

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I988492ccecbc3f64a5153b381c4a97b8a0181f52
2020-03-05 22:10:41 +02:00