andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
6,172 Commits 2 Branches 52 Tags 32 MiB
Commit Graph

14 Commits

Author SHA1 Message Date
Hadi Asyrafi 1520b5d688 intel: Refactor common platform code [5/5] 
Removes unused source code for BL2 and BL31 in platform.mk.
Clean-up unused header files, syntax fixes, and alphabetical
sorting post-refactoring

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd
 2019-11-28 12:47:58 +08:00
Hadi Asyrafi d09adcbaf2 intel: Refactor common platform code [3/5] 
Pull out mailbox driver into common area as they can be shared between
intel's socfpga platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
 2019-11-28 12:47:58 +08:00
Hadi Asyrafi e9b5e360de intel: Refactor common platform code [2/5] 
Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
 2019-11-28 12:47:58 +08:00
Hadi Asyrafi 328718f254 intel: Refactor common platform code [1/5] 
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
 2019-11-28 12:47:57 +08:00
Hadi Asyrafi fea24b88e4 intel: stratix10: Fix reliance on hard coded clock information 
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
 2019-08-13 18:20:53 +08:00
Hadi Asyrafi 3f7b1490dc intel: Platform common code refactor 
Pull out common code from aarch64 and include

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
 2019-08-07 12:19:11 +00:00
Hadi Asyrafi bf719f66a7 intel: Pull out common drivers into platform common 
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib79e2c6fe6e66dec5004701133ad6a5f4c78f2fa
 2019-06-26 18:45:01 +08:00
Muhammad Hadi Asyrafi Abdul Halim 10e70f87e0 intel: Enable watchdog timer on Intel S10 platform 
Watchdog driver support & enablement during platform setup

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
 2019-03-21 10:35:24 +08:00
Muhammad Hadi Asyrafi Abdul Halim f5ba408c34 intel: QSPI boot enablement 
Manages QSPI initialization, configuration and IO handling as boot device

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
 2019-03-13 10:17:14 +08:00
Dimitris Papastamos 3c652a2d1c
Merge pull request #1863 from thloh85-intel/mmc_fixes 
drivers: mmc: Fix some issues with MMC stack
 2019-03-08 09:41:22 +00:00
Tien Hock, Loh dd8c03b6bf plat: intel: Add MMC OCR voltage information for initialization 
MMC stack needs OCR voltage information for the platform to initialize
MMC controller correctly.

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
 2019-03-08 09:26:24 +08:00
Muhammad Hadi Asyrafi Abdul Halim 5bd1b445a9 intel: Mailbox service un-accessible 
Change map region for device 2 from non-secure to secure

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
 2019-03-07 13:17:25 +08:00
Loh Tien Hock 51f366ac85 plat: intel: Fix faulty DDR calibration value 
A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
 2019-02-13 14:39:31 +08:00
Loh Tien Hock 9d82ef26c6 plat: intel: Add BL2 support for Stratix 10 SoC 
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
 2019-02-04 16:17:24 +08:00