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8 Commits

Author SHA1 Message Date
Hadi Asyrafi 1520b5d688 intel: Refactor common platform code [5/5] 
Removes unused source code for BL2 and BL31 in platform.mk.
Clean-up unused header files, syntax fixes, and alphabetical
sorting post-refactoring

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd
 2019-11-28 12:47:58 +08:00
Hadi Asyrafi d09adcbaf2 intel: Refactor common platform code [3/5] 
Pull out mailbox driver into common area as they can be shared between
intel's socfpga platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
 2019-11-28 12:47:58 +08:00
Hadi Asyrafi e9b5e360de intel: Refactor common platform code [2/5] 
Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
 2019-11-28 12:47:58 +08:00
Hadi Asyrafi 328718f254 intel: Refactor common platform code [1/5] 
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
 2019-11-28 12:47:57 +08:00
Sandrine Bailleux 5119fa7b8d Merge changes from topic "intel-plat-refactor" into integration 
* changes:
  intel: Platform common code refactor
  intel: Platform common code refactor
 2019-08-07 14:20:01 +00:00
Hadi Asyrafi 3f7b1490dc intel: Platform common code refactor 
Pull out common code from aarch64 and include

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
 2019-08-07 12:19:11 +00:00
Hadi Asyrafi 600db4e338 intel: stratix10: Fix BL31 memory mapping 
Previous config blocks ATF runtime service communications with SDM mailbox

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ia857facd0bd0790056df94ed1e016bcf619a161e
 2019-08-02 20:16:32 +08:00
Tien Hock, Loh 1cf55aba49 plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform 
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
 2019-02-26 09:25:14 +08:00