This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.
* SGI 8 as the source IRQ
* Special Private Event 0
* Three private, dynamic events
* Three shared, dynamic events
* Twelve general purpose explicit events
Verified using TFTF SDEI test suite.
******************************* Summary *******************************
Test suite 'SDEI' Passed
=================================
Tests Skipped : 0
Tests Passed : 5
Tests Failed : 0
Tests Crashed : 0
Total tests : 5
=================================
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390
This patch enables the Exception Handling Framework to service the WDT
interrupts on all Tegra platforms.
Verified that the watchdog timer interrupt fires after migrating to
the EHF.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6b2e33da7841aa064e3a8f825c26fadf168cd0d5
This patch removes usage of bakery_locks from the FIQ handler, as it
creates unnecessary dependency whenever the watchdog timer interrupt
fires. All operations inside the interrupt handler are 'reads', so
no need for serialization.
Change-Id: I3f675e610e4dabc5b1435fdd24bc28e424f5a8e4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Renamed the structure according to a SPMD refactoring
introduced in <c585d07aa> since this structure is used
to service both EL1 and EL2 as opposed to serving only EL1.
Change-Id: I23b7c089e53f617157a4b4e6443acce50d85c3b5
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING
configuration variable and is only enabled for Tegra210 platforms, for now.
Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch updates the secure interrupt handler to mark the interrupt
as complete in case the NS world has not registered a handler.
Change-Id: Iebe952305f7db46375303699b6150611439475df
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Macro assert(e) request 'e' is a bool type, if useing other
type, MISRA report a "The Essential Type Model" violation,
Add a judgement to fix the defects, if 'e' is not bool type.
Remove unused code [Rule 2.5]
Fix the essential type model violation [Rule 10.6, 10.7]
Use local parameter to raplace function parameter [Rule 17.8]
Change-Id: Ifce932addbb0a4b063ef6b38349d886c051d81c0
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This patch adds (void) for unused function parameters to
fix Rule 2.7 of the MISRA standard.
Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
- Migrate to bl31_early_platform_setup2().
- Remove references to removed build options.
- Replace zeromem16() by zeromem().
- Use private definition of bl31_params_t.
This is an incomplete migration, the platform doesn't currently compile.
Change-Id: I67fbf2206678be80c3a16692024221a131cec42f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Main fixes:
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Convert object type to match the type of function parameters
[Rule 10.3]
* Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses[Rule 20.7]
Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.
NOTE: Files that have been imported by FreeBSD have not been modified.
[0]: https://spdx.org/
Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
This patch modifies the secure IRQ registration process to allow platforms
to specify the target CPUs as well as the owner of the IRQ. IRQs "owned"
by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted
OS would return INTR_TYPE_S_EL1 as a result.
Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.
The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.
Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
Max Shvetsov
Anthony Zhou
Antonio Nino Diaz
dp-arm