Commit Graph

10689 Commits

Author SHA1 Message Date
Sandrine Bailleux d08c496699 docs(threat-model): make measured boot out of scope
Add an explicit note that measured boot is out of scope of the threat
model. For example, we have no threat related to the secure
management of measurements, nor do we list its security benefits
(e.g. in terms of repudiation).

This might be a future improvement to the threat model but for now
just acknowledge it is not considered.

Change-Id: I2fb799a2ef0951aa681a755a948bd2b67415d156
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-19 11:31:39 +02:00
Sandrine Bailleux 3d6cc21066 docs(threat-model): revamp threat #9
Reword the description of threat #9 to make it more future-proof for
Arm CCA. By avoiding specific references to secure or non-secure
contexts, in favour of "worlds" and "security contexts", we make the
description equally applicable to 2-world and 4-world architectures.

Note that there are other threats that would benefit from such a
similar revamp but this is out of scope of this patch.

Also list malicious secure world code as a potential threat
agent. This seems to be an oversight in the first version of the
threat model (i.e. this change is not related to Arm CCA).

Change-Id: Id8c8424b0a801104c4f3dc70e344ee702d2b259a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Sandrine Bailleux 1b7c82cafe docs(threat-model): remove some redundant text in threat #08
The threat description was repeating the threat title.

Change-Id: I67de2c0aab6e86bf33eb91e7562e075fcb76259b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Sandrine Bailleux 4365b30ccf docs(threat-model): make experimental features out of scope
By nature, experimental features are incomplete pieces of work,
sometimes going under rapid change. Typically, the threat model
implications have not been fully considered yet.

Change-Id: Ice8d4273a789558e912f82cde592da4747b37fdf
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Sandrine Bailleux f10dd3e039 docs(threat-model): cosmetic changes
- Add empty lines after titles.

 - Reduce number of highlighting characters to fit title length.

 - Remove most ``monospaced text``.
   I think most of it looked weird in the rendered HTML version and
   it had no obvious meaning.

Change-Id: I5f746a3de035d8ac59eec0af491c187bfe86dad7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Sandrine Bailleux 50075fdcfb build(changelog): add new scope for the threat model
Change-Id: I884f31f7f4b5515c420839ff37d401faa69f5fff
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-17 10:01:11 +02:00
Madhukar Pappireddy a921da5ed2 Merge changes If2408af3,If485ff27 into integration
* changes:
  feat(versal): add SMCCC call TF_A_PM_REGISTER_SGI
  feat(versal): add support to reset SGI
2022-05-13 18:13:33 +02:00
Olivier Deprez 0dc2b51681 Merge changes from topic "ns/save_fpregs_context" into integration
* changes:
  feat(sgi): enable fpregs context save and restore
  feat(spm_mm): add support to save and restore fp regs
2022-05-13 17:28:58 +02:00
Sandrine Bailleux 6aed554954 Merge changes from topic "rss/mboot-attest" into integration
* changes:
  docs(maintainers): add PSA, MHU, RSS comms code owners
  feat(plat/arm/fvp): enable RSS backend based measured boot
  feat(lib/psa): mock PSA APIs
  feat(drivers/measured_boot): add RSS backend
  feat(drivers/arm/rss): add RSS communication driver
  feat(lib/psa): add initial attestation API
  feat(lib/psa): add measured boot API
  feat(drivers/arm/mhu): add MHU driver
2022-05-13 16:15:35 +02:00
Joanna Farley aa69de86f0 Merge changes I50721040,I1ce4b7b4,I9658aef7,I40ff55eb into integration
* changes:
  fix(intel): remove unused printout
  fix(intel): fix configuration status based on start request
  style(intel): align the sequence in header file
  fix(intel): remove redundant NOC header declarations
2022-05-13 14:29:24 +02:00
David Vincze c671daeeea docs(maintainers): add PSA, MHU, RSS comms code owners
Adding Sandrine Bailleux for the PSA APIs and myself for the
MHU and RSS comms drivers as code owner.

Change-Id: Ib948479cc6e46163aae59c938877a2d0bcf91754
Signed-off-by: David Vincze <david.vincze@arm.com>
2022-05-13 11:20:05 +02:00
Sieu Mun Tang 0d19eda0dd fix(intel): remove unused printout
This patch is to remove unused printout.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I507210402dcbaf8369209308ae1fcedaccb0292d
2022-05-13 16:46:25 +08:00
Sieu Mun Tang 673afd6f8e fix(intel): fix configuration status based on start request
This patch is to fix configuration status command now returns
the result based on the last config start command made to the
runtime software. The status type can be either:
- NO_REQUEST (default)
- RECONFIGURATION
- BITSTREAM_AUTH

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1ce4b7b4c741d88de88778f8fbed7dfe83a39fbc
2022-05-13 16:46:20 +08:00
Sieu Mun Tang 762c34a85d style(intel): align the sequence in header file
This patch is to align the sequence of function in header file.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9658aef78b06b744c6c14f95b2821daf5dbb0082
2022-05-13 16:46:17 +08:00
Sieu Mun Tang 58690cd629 fix(intel): remove redundant NOC header declarations
This patch is to remove redundant NOC declarations in
system manager header file. The NOC headers are shareable
across both Stratix 10 and Agilex platforms.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I40ff55eb1d8fe280db1d099d5d1a3c2bf4b4b459
2022-05-13 16:46:12 +08:00
Tanmay Shah fcf6f46931 feat(versal): add SMCCC call TF_A_PM_REGISTER_SGI
This call is used to register and reset SGI interrupt.
Before this functionality was performed using IOCTL_REGISTER_SGI
pm_ioctl EEMI call. It's not correct use of PM_IOCTL as it is
not EEMI functionality. Instead this new SMCCC call will be
handled by TF-A specific handler.

Change-Id: If2408af38b889d29a5c584e8eec5f1672eab4fb5
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-05-12 20:29:41 +02:00
Venkatesh Yadav Abbarapu bf70449ba2 feat(versal): add support to reset SGI
Add "reset" parameter in pm_register_sgi() to reset
SGI number. This will be required if OS wants to reset
SGI number to default state. Caller can reset param to
1 to reset SGI in ATF.

Change-Id: If485ff275df884f74eb67671cac7fa953458afe9
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-05-12 20:29:03 +02:00
Madhukar Pappireddy 15e498de74 Merge "fix(security): workaround for CVE-2022-23960" into integration 2022-05-12 20:24:10 +02:00
Madhukar Pappireddy 1d41fffff7 Merge "docs(versal): fix the versal platform emu name" into integration 2022-05-12 16:49:36 +02:00
Madhukar Pappireddy b57ccdf918 Merge "fix(errata): workaround for DSU-110 erratum 2313941" into integration 2022-05-12 16:34:40 +02:00
Madhukar Pappireddy 868f9768bb Merge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration
* changes:
  fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
  fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
  fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
  fix(intel): extending to support large file size for AES encryption and decryption
  feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
  feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
  fix(intel): update certificate mask for FPGA Attestation
  feat(intel): update to support maximum response data size
  feat(intel): support ECDSA HASH Verification
  feat(intel): support ECDSA HASH Signing
  feat(intel): support ECDH request
  feat(intel): support ECDSA SHA-2 Data Signature Verification
  feat(intel): support ECDSA SHA-2 Data Signing
  feat(intel): support ECDSA Get Public Key
  feat(intel): support session based SDOS encrypt and decrypt
  feat(intel): support AES Crypt Service
  feat(intel): support HMAC SHA-2 MAC verify request
  feat(intel): support SHA-2 hash digest generation on a blob
  feat(intel): support extended random number generation
  feat(intel): support crypto service key operation
  feat(intel): support crypto service session
  feat(intel): extend attestation service to Agilex family
  fix(intel): flush dcache before sending certificate to mailbox
  fix(intel): introduce a generic response error code
  fix(intel): allow non-secure access to FPGA Crypto Services (FCS)
  feat(intel): single certificate feature enablement
  feat(intel): initial commit for attestation service
  fix(intel): update encryption and decryption command logic
2022-05-12 16:19:15 +02:00
Madhukar Pappireddy 1f0309d498 Merge "fix(zynqmp): define and enable ARM_XLAT_TABLES_LIB_V1" into integration 2022-05-12 16:14:55 +02:00
Bipin Ravi c2a15217c3 fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex Makalu/Makalu-ELP/Hunter
and Neoverse Demeter/Poseidon.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f6689b662ecac92491e0c0902df4270051ce5b
2022-05-11 19:05:48 +02:00
Bipin Ravi 7e3273e8e4 fix(errata): workaround for DSU-110 erratum 2313941
DSU-110 erratum 2313941 is a Cat B erratum and applies to revisions
r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open.

The workaround sets IMP_CLUSTERACTLR_EL1[16:15] bits to 0b11 to disable
clock gating of the SCLK domain. This will increase the idle power
consumption.

This patch applies the fix for Cortex-X2/A510/A710 and Neoverse N2.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1781796/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I54d948b23e8e01aaf1898ed9fe4e2255dd209318
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2022-05-11 19:05:36 +02:00
Nishant Sharma 18fa43f753 feat(sgi): enable fpregs context save and restore
This is required to prevent Nwd context corruption during StMM
execution.

Standalone MM uses OpenSSL for secure boot, which uses FP registers for
floating point calculations.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I6ed11d4fa5d64c3089a24b66fd048a841c480792
2022-05-11 17:18:21 +01:00
Nishant Sharma 15dd6f19da feat(spm_mm): add support to save and restore fp regs
Add the support to save Nwd's floating point registers before switching
to SEL0 and then restore it after coming out of it. Emit a warning
message if SPM_MM is built with CTX_INCLUDE_FPREGS == 0

There is no need to save FP registers of SEL0 because secure partitions
run to completion.

This change is used to prevent context corruption if secure partition
enabled and Nwd decide to use floating point registers.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I1eea16ea2311a4f00a806ea72c118752821b9abb
2022-05-11 17:18:21 +01:00
Madhukar Pappireddy 15ff61f5ce Merge changes from topic "fix_st_spi" into integration
* changes:
  fix(st-spi): remove SR_BUSY bit check before sending command
  fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()
2022-05-11 17:31:44 +02:00
Madhukar Pappireddy bf61c4f0af Merge "docs: update release and code freeze dates" into integration 2022-05-11 17:16:48 +02:00
Bipin Ravi 401cb4bb76 Merge "fix(security): workaround for CVE-2022-23960 for Cortex-X1" into integration 2022-05-11 16:59:15 +02:00
Bipin Ravi c8c7c47bb3 Merge "fix(errata): workarounds for cortex-x1 errata" into integration 2022-05-11 16:59:00 +02:00
Bipin Ravi 123cebe5db Merge "feat(cpu): add support for Cortex-X1" into integration 2022-05-11 16:58:50 +02:00
Tamas Ban c44e50b725 feat(plat/arm/fvp): enable RSS backend based measured boot
Enable the RSS backend based measured boot feature.
In the absence of RSS the mocked version of PSA APIs
are used. They always return with success and hard-code data.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I7543e9033a7a21f1b836d911d8d9498c6e09b956
2022-05-11 15:47:32 +02:00
Tamas Ban 0ce2072d9b feat(lib/psa): mock PSA APIs
Introduce PLAT_RSS_NOT_SUPPORTED build config to
provide a mocked version of PSA APIs. The goal is
to test the RSS backend based measured boot and
attestation token request integration on such
a platform (AEM FVP) where RSS is otherwise
unsupported. The mocked PSA API version does
not send a request to the RSS, it only returns
with success and hard-coded values.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ice8d174adf828c1df08fc589f0e17abd1e382a4d
2022-05-11 15:47:30 +02:00
Tamas Ban 0442ebd2e9 feat(drivers/measured_boot): add RSS backend
Runtime Security Subsystem (RSS) provides for the host:
- Runtime service to store measurments, which were
  computed by the host during measured boot.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ia9e4e8a1fe8f01a28da1fd8c434b780f2a08f94e
2022-05-11 15:47:02 +02:00
Tamas Ban ce0c40edc9 feat(drivers/arm/rss): add RSS communication driver
This commit adds a driver to conduct the AP's communication
with the Runtime Security Subsystem (RSS).
RSS is Arm's reference implementation for the CCA HES [1].
It can be considered as a secure enclave to which, for example,
certain services can be offloaded such as initial attestation.

RSS comms driver:
 - Relies on MHU v2.x communication IP, using a generic MHU API,
 - Exposes the psa_call(..) API to the upper layers.

[1] https://developer.arm.com/documentation/DEN0096/latest

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: Ib174ac7d1858834006bbaf8aad0eb31e3a3ad107
2022-05-11 15:47:02 +02:00
Tamas Ban 084856513d feat(lib/psa): add initial attestation API
Supports:
 - Get Platform Attestation token from secure enclave

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Icaeb7b4eaff08e10f449fbf752068de3ac7974bf
2022-05-11 15:47:02 +02:00
Tamas Ban 758c64715b feat(lib/psa): add measured boot API
A secure enclave could provide an alternate
backend for measured boot. This API can be used
to store measurements in a secure enclave, which
provides the measured boot runtime service.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I2448e324e7ece6b318403c5937dfe7abea53d0f3
2022-05-11 15:47:02 +02:00
Tamas Ban af26d7d6f0 feat(drivers/arm/mhu): add MHU driver
The Arm Message Handling Unit (MHU) is a mailbox controller used to
communicate with other processing element(s). Adding a driver to
enable the communication:
- Adding generic MHU driver interface,
- Adding MHU_v2_x driver.

Driver supports:
 - Discovering available MHU channels,
 - Sending / receiving words over MHU channels,
 - Signaling happens over a dedicated channel.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: I41a5b968f6b8319cdbdf7907d70bd8837839862e
2022-05-11 15:47:02 +02:00
Okash Khawaja e81e999b9d fix(security): workaround for CVE-2022-23960 for Cortex-X1
Implements the loop workaround for Cortex-X1.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I5828a26c1ec3cfb718246ea5c3b099dabc0fb3d7
2022-05-11 15:24:37 +02:00
Okash Khawaja 7b76c20d8e fix(errata): workarounds for cortex-x1 errata
This patch adds workarounds for following cortex-x1 errata:

- 1821534 (CatB)
- 1688305 (CatB)
- 1827429 (CatB)

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401782/latest

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I10ebe8d5c56a6d273820bb2c682f21bf98daa7a5
2022-05-11 15:24:29 +02:00
Okash Khawaja 6e8eca78e5 feat(cpu): add support for Cortex-X1
This patch adds basic CPU library code to support Cortex-X1 CPU in TF-A.
Follow-up patches will add selected errata workarounds for this CPU.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I4a3d50a98bf55a555bfaefeed5c7b88a35e3bc21
2022-05-11 15:24:20 +02:00
Daniel Boulby 06c6f6536f docs: update release and code freeze dates
Change-Id: I72d200a0cfbcb4ef53b732faa5b7125dce91395d
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2022-05-11 11:59:14 +01:00
Sieu Mun Tang ac097fdf07 fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
This patch is to add flash dcache after return
response in INTEL_SIP_SMC_MBOX_SEND_CMD.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie9451e352f2b7c41ebb44a1f6be9da35f4600fb9
2022-05-11 17:46:00 +08:00
Sieu Mun Tang 70a7e6af95 fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
This patch is to extend to support large file size
for SHA2/HMAC get digest and verifying. The large
file will be split into smaller chunk and send using
initialize, update and finalize staging method.

Signed-off-by: Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1815deeb61287b32c3e77c5ac1b547b79ef12674
2022-05-11 17:45:57 +08:00
Sieu Mun Tang 1d97dd74cd fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
This patch is to extend to support large file size
for SHA-2 ECDSA data signing and signature verifying.
The large file will be split into smaller chunk and
send using initialize, update and finalize staging method.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: If277b2b375a404fe44b0858006c8ba6316a5ce23
2022-05-11 17:45:55 +08:00
Sieu Mun Tang dcb144f1fb fix(intel): extending to support large file size for AES encryption and decryption
This patch is to extend to support large file size
for AES encryption and decryption. The large file
will be split into smaller chunk and send using
initialize, update and finalize staging method.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie2ceaf247e0d7082aad84faf399fbd18d129c36a
2022-05-11 17:45:50 +08:00
Sieu Mun Tang c436707bc6 feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
A separated SMC function ID of mailbox command
is introduced for the new format of SMC protocol.

The new format of SMC procotol will be started
using by Zephyr.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I7996d5054f76c139b5ad55451c373f5669a1017f
2022-05-11 17:45:37 +08:00
Sieu Mun Tang ad47f1422f feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
A separated SMC function ID of non-mailbox command
is introduced for the new format of SMC protocol.

The new format of SMC procotol will be started
using by Zephyr.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I01cff2739364b1bda2ebb9507ddbcef6095f5d29
2022-05-11 17:43:16 +08:00
Boon Khai Ng fe5637f27a fix(intel): update certificate mask for FPGA Attestation
Update the certificate mask to 0xff to cover all certificate
in Agilex family.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id40bc3aa4b3e4f7568a58581bbb03a75b0f20a0b
2022-05-11 16:57:37 +08:00
Sieu Mun Tang b703facaaa feat(intel): update to support maximum response data size
Update to support maximum (4092 bytes) response data size.
And, clean up the intel_smc_service_completed function to
directly write the response data to addr to avoid additional
copy.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I0a230e73c563d22e6999ad3473587b07382dacfe
2022-05-11 16:57:34 +08:00