Add pin control support for RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I08719015cab1ec59e2270523980a0a3e26e72c01
Add support for initializing DRAM on RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I99f1a6971a061a44687af498d55306a93e4fc8f7
Move DDR/QoS/PFC header files, so that the same code
can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I2cc0ceda8d05b6b8d95a69afdc233dc0d098e850
Move rpc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I04805d720d95b8edcc14e652f897fadc7f432197
Move avs driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I85d9fa8b6abf158ce2521f1696478f7c5339fc42
Move authentication driver code to common directory, so that the
same code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I02592dfc714998bf89b9feaa78f685ae36be6f59
Move dma driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Idce2e2f4e098cfc17219f963373d20ebf74e5b7c
Move watch driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I235f2cde325a0feeadbfc4b7ee02e8b1186f7ea1
Move rom driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I399dfb5eff186db76d26fa9c54bea88bee66789c
Move delay driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I5e806bd0e0a0a4b436048513b7089db90ff9805f
Move console/scif driver code to common directory, so that the
same code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I0b15e4f4ffaaa99e77bcee32b1dad648eeadcd9b
Move pwrc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I75d91a44d872fe2296b15c700efacd5721385363
Move io driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ic661e415c91a1fbfd5eee3bba86466037e51574b
Move eMMC driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I7f3055709337327d1a1c9f563c14ad1626adb355
Move plat common sources to common directory, so that same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Id2b1822c97cc50e3febaffc2e5f42b4d53809a17
Create a common directory and move the header and assembly files
so that the common code can be used by both Renesas R-Car Gen3 and
RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ia9a563a1c3c9f8c6f0d3cb82622deb2e155d7f6c
Write char if fifo is empty. If this is done like this all chars are
printed. Because origin code just put that chars to fifo and in case of
reset messages were missing.
Before this change chars are put to fifo and only check before adding if
fifo is full. The patch is changing this logic that it is adding char only
when fifo is empty to make sure that in case of reset (by another SW for
example) all chars are printed. Maybe one char can be missed but for IP
itself it is much easier to send just one char compare to full fifo.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ic24c2c1252bce24be2aed68ee29477ca4a549e5f
This patch fixes checkpatch warnings and arrange header
as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I46cd4d9b2851202324fe714e776cf3ad2ee1d923
Sort the headers alphabetically and replace TAB with a space
after #define.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I07c358294b7c02cbfa360112bbbde0eb5f2b50f5
This patches fixes checkpatch warnings, replace TAB with space
after #define macros and arrange header as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iba009587e0b499b3ae58876be390602ae14175b2
Fix checkpatch warnings.
There are no functional changes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iec7dd019bd38e84eccd8cc17189745fdef1911bb
This patch fixes the below checkpatch warnings
Line 13: WARNING: please, no spaces at the start of a line
Line 15: WARNING: please, no spaces at the start of a line
Line 18: WARNING: Missing a blank line after declarations
Line 24: WARNING: please, no spaces at the start of a line
Line 26: WARNING: please, no spaces at the start of a line
Line 29: WARNING: Missing a blank line after declarations
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I41d146e86889640d11e88c0717039353ddceff0d
Fix checkpatch warnings.
There are no functional changes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ic7406aa88e121914270a8d192f170c9c4244578a
Use space instead of TAB after #define's. Also updated
header files as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I4eac94f0bc79f24b8ac7165ec48f1e1de95d7205
Replace TAB with space after #define macros and update comments as per
TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iff46838a41f991f7dd9dc6fb043e9e482ea0b11d
Sort the header includes alphabetically, fix typos and drop unneeded TAB
and replace it with space
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I62e2658b0309c0985dd32ff023b8b16bd7f2be8e
Implementation is simple, just wait for the TX FIFO to be empty.
Without this patch TF-A on A3720 truncate the last line:
NOTICE: BL31: Built : 16:1
With this patch TF-A on A3720 print correctly also the last line:
NOTICE: BL31: Built : 19:03:31, Dec 23 2020
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2f2ea42beab66ba132afdb400ca7898c5419db09
Fix checkpatch warnings and MISRA defects.
There are no functional changes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I349a8eaa7bd6182746ba5104ee9fe48a709c24fd
The BL31 log driver is registered before the xlat tables are initialized,
at that point the log memory is configured as device memory and can only
be accessed with up-to-32bit aligned accesses. Adjust the driver to do
just that.
The memset() call has to be replaced by a loop of 32bit writes to the log,
the memcpy() is trivial to replace with a single 32bit write of the entire
TLOG word. In the end, this even simplifies the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie9152e782e67d93e7236069a294df812e2b873bf
* changes:
docs: update STM32MP1 with versions details
stm32mp1: get peripheral base address from a define
stm32mp1: add finished good variant in board identifier
Retrieve peripheral base address from a define instead of
parsing the device tree. The goal is to improve execution time.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Chip select is retrieved from device tree and check
must be done regarding the MAX_CS defined.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Change-Id: I03144b133bd51a845a4794f0f6bbd9402fc04936
FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.
Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
In the function gicv2_set_spi_routing, the signed value proc_num is cast
to unsigned int before being compared to other unsigned values in two
assert calls. The value proc_num can be a negative value, and once the
negative value is cast to unsigned it becomes a very large number which
will trigger the assert. This patch changes the assert cast so that the
unsigned values are cast to signed instead, keeping the same functionality
but allowing proc_num to be negative.
This bug can be seen when running the SDEI RM_ANY routing mode test in
TFTF on the Juno platform.
This patch also makes the usage of the proc_num variable in other gicv2
functions more clear.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If1b98eebb00bd9b73862e5e995e5e68c168170a6
And from crash_console_flush.
We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.
Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Clear interrupt flag register after each sector read to avoid
issue when checking the register status.
Without clearing the interrupt, the status read doesn't wait
properly the ready bit.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: If290e3f165b986f0e736bb1b5e4d3dad4b749d74
The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.
Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.
Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should
be toggled in addition to the XFI/SFI PHY reset.
Change-Id: Idd2c2abfcb2f960caa01e6d69db524c2e4734f50
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Do not force non-secure access level for PIDI masters when LLC_SRAM
is enabled. The EIP197 is located on CP0 and need to access secure
SRAM in AP LLC. This requires EIP197 DMA to have AXPROT[1]=0 and not
changed when forwarded to address decoding tables.
Change-Id: I8962db94a124350c14220ba6d0364d294ae4664a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Added ccu window to allow access to addresses
in the range [0xf100_0000, 0xf1ff_ffff].
Change-Id: I63ee68338d674114d01cd627198dc907653493e8
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Biju Das
Manish Pandey
Madhukar Pappireddy
Michal Simek
Pali Rohár
Marek Vasut
Joanna Farley
Mark Dykes
Yann Gautier
Jimmy Brisson
Lionel Debieve
Christophe Kerello
johpow01
Grzegorz Jaszczyk
Marcin Wojtas
Konstantin Porotchkin
Alex Leibovich