Commit Graph

10637 Commits

Author SHA1 Message Date
Sandrine Bailleux 71a5543bcf docs(prerequisites): update Arm compilers download link
Right now, TF-A documentation recommends downloading Arm compilers
from:

  https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads

However, this page is now deprecated, as indicated by the banner at
the top of the page. When navigating to the new recommended page, one
can see the following note, which provides the rationale for the
deprecation:

  GNU Toolchain releases from Arm were published previously as two
  separate releases - one for A-profile and the other for R & M
  profiles (GNU Toolchain for A-profile processors and GNU Arm
  Embedded Toolchain).

  Arm GNU Toolchain releases unifies these two into a single release
  and the previous way of releases therefore have been
  discontinued. However, the previous releases will continue to be
  available for reference.

This patch updates the link to the new recommended place for compiler
downloads.

Change-Id: Iefdea3866a1af806a5db2d2288edbb63c543b8ee
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-04-25 08:19:44 +02:00
Sandrine Bailleux 94909893df Merge "docs: fix mailing lists URLs" into integration 2022-04-25 07:58:46 +02:00
anans 50593e696e refactor(ufs): adds a function for fdeviceinit
time taken for device init varies based on different devices,
instead of waiting for 200ms - we can poll on fdevice init
until it gets cleared, similar to what linux does

Change-Id: I571649231732fde0cd6d5be89b6f14fe905fcaff
Signed-off-by: anans <anans@google.com>
2022-04-25 05:47:35 +02:00
Sieu Mun Tang 5ca81820de docs(intel): add Sieu Mun and Benjamin Jit Loon as maintainers
Add Sieu Mun Tang and Benjamin Jit Loon Lim as new
Intel SocFPGA platform maintainers and remove the
rest of the Intel SocFPGA platform maintainers.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ieb9a35e278d70a12351aaccab90ddc7be09dc861
2022-04-23 09:50:35 +08:00
Olivier Deprez 65b13bace4 Merge changes from topic "ffa_el3_spmc" into integration
* changes:
  feat(spmc): add support for direct req/resp
  feat(spmc): add support for handling FFA_ERROR ABI
  feat(spmc): add support for FFA_MSG_WAIT
  feat(spmc): add function to determine the return path from the SPMC
  feat(spmd): enable handling of FF-A SMCs with the SPMC at EL3
  feat(spmd): update SPMC init flow to use EL3 implementation
  feat(spmc): add FF-A secure partition manager core
  feat(spmc): prevent read only xlat tables with the EL3 SPMC
  feat(spmc): enable building of the SPMC at EL3
  refactor(spm_mm): reorganize secure partition manager code
2022-04-22 21:09:13 +02:00
Manish Pandey 115748b209 Merge "fix(stm32mp1): correct dtc version check" into integration 2022-04-22 17:22:59 +02:00
Yann Gautier 429f10e336 fix(stm32mp1): correct dtc version check
Depending on the shell used, the grep command can fail, leading to
a wrong dtc version detection. Correct that by adding quotes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I329ec929559c94bf1bf99b127662c9d978e067cf
2022-04-22 13:23:22 +02:00
Olivier Deprez 6f8674964b Merge "feat(spm): add FFA_RX_ACQUIRE forwarding in SPMD" into integration 2022-04-21 11:35:42 +02:00
Sandrine Bailleux f4a55e6b32 docs: fix mailing lists URLs
With the transition to mailman3, the URLs of TF-A and TF-A Tests
mailing lists have changed. However, we still refer to the old
location, which are now dead links.

Update all relevant links throughout the documentation.

There is one link referring to a specific thread on the TF-A mailing
list in the SPM documentation, for which I had to make a guess as to
what's the equivalent mailman3 URL. The old URL scheme indicates that
the thread dates from February 2020 but beyond that, I could not make
sense of the thread id within the old URL so I picked the most likely
match amongst the 3 emails posted on the subject in this time period.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Reported-by: Kuohong Wang <kuohong.wang@mediatek.com>
Change-Id: I83f4843afd1dd46f885df225931d8458152dbb58
2022-04-21 10:26:23 +02:00
Marc Bonnici 9741327df5 feat(spmc): add support for direct req/resp
Enable the SPMC to handle FFA_MSG_SEND_DIRECT_REQ and
FFA_MSG_SEND_DIRECT_RESP ABIs.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ia196c7405993f600e4fdbf467397ea3fb035a62a
2022-04-20 19:40:31 +01:00
Marc Bonnici d663fe7a30 feat(spmc): add support for handling FFA_ERROR ABI
This ABI is only valid during SP initialisation to indicate
failure. If this occurs during SP initialisation signal a failure,
otherwise respond with a not supported error code.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I0182a1641c0f6850e82173af333be79b594f2318
2022-04-20 19:40:31 +01:00
Marc Bonnici c4db76f066 feat(spmc): add support for FFA_MSG_WAIT
Handle an incoming call of FFA_MSG_WAIT from the secure world
and update the runtime state of the calling partition accordingly.

This ABI can be called in the following scenarios:
  - Used by an SP to signal it has finished initializing.
  - To resume the normal world after handling a secure interrupt
    that interrupted the normal world.
  - To relinquish control back to the normal world.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I929713a2280e8ec291b5b4e8f6d4b49df337228c
2022-04-20 19:40:31 +01:00
Marc Bonnici 20fae0a7ce feat(spmc): add function to determine the return path from the SPMC
Use knowledge of the target partition ID and source security state
to determine which route should be used to exit the SPMC.

There are 3 exit paths:
1) Return to the normal world via the SPMD, this will take care of
   switching contexts if required.
2) Return to the secure world when the call originated in the normal
   world and therefore switch contexts.
3) Return to the secure world when the call originated in the secure
   world, therefore we can return directly.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I4037f3a8a8519e2c9f1876be92806d2c41d0d154
2022-04-20 19:40:31 +01:00
Marc Bonnici bb01a67306 feat(spmd): enable handling of FF-A SMCs with the SPMC at EL3
Any FF-A SMC that arrives from the normal world is handled by the
SPMD before being forwarded to the SPMC. Similarly any SMC
arriving from the secure world will hit the SPMC first and be
forwarded to the SPMD if required, otherwise the SPMC will
respond directly.

This allows for the existing flow of handling FF-A ABI's when
the SPMC resides at a lower EL to be preserved.

In order to facilitate this flow the spmd_smc_forward function
has been split and control is either passed to the SPMC or it is
forwarded as before. To allow this the flags and cookie parameters
must now also be passed into this method as the SPMC must be able to
provide these when calling back into the SPMD handler as appropriate.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I84fee8390023295b9689067e14cd25cba23ca39b
2022-04-20 19:40:28 +01:00
Marc Bonnici 6da76075bf feat(spmd): update SPMC init flow to use EL3 implementation
Allow the SPMD to initialise an SPMC implementation at EL3 directly
rather than at a lower EL.
This includes removing the requirement to parse an SPMC manifest to
obtain information about the SPMC implementation, in this case since the
SPMD and SPMC reside in the same EL we can hardcode the required
information directly.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I66d1e1b3ec2d0abbfc28b011a32445ee890a331d
2022-04-20 18:29:32 +01:00
Marc Bonnici 5096aeb2ba feat(spmc): add FF-A secure partition manager core
This patch introduces the core support for enabling an SPMC in EL3
as per the FF-A spec.

The current implemented functionality is targeted to enable
initialization of the SPMC itself and initial support for
bringing up a single S-EL1 SP.

This includes initialization of the SPMC's internal state,
parsing of an SP's manifest, preparing the cpu contexts and
appropriate system registers for the Secure Partition.

The spmc_smc_handler is the main handler for all incoming SMCs
to the SPMC, FF-A ABI handlers and functionality will
be implemented in subsequent patches.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ib33c240b91e54cbd018a69fec880d02adfbe12b9
2022-04-20 18:29:30 +01:00
Joanna Farley e96ffdc8b4 Merge "fix(errata): workaround for Cortex-X2 erratum 2147715" into integration 2022-04-19 17:07:49 +02:00
Manish Pandey dfc59a7b82 Merge changes from topic "st_nvmem_layout" into integration
* changes:
  refactor(stm32mp1-fdts): remove nvmem_layout node
  refactor(stm32mp1): drop the "st,stm32-nvmem-layout" node
  refactor(st): remove useless includes
2022-04-19 16:11:24 +02:00
Manish Pandey 38b7828e1a Merge "refactor(ufs): delete unused variables" into integration 2022-04-19 11:51:12 +02:00
Jayanth Dodderi Chidanand 781d07a421 refactor(twed): improve TWED enablement in EL-3
The current implementation uses plat_arm API under generic code.
"plat_arm" API is a convention used with Arm common platform layer
and is reserved for that purpose. In addition, the function has a
weak definition which is not encouraged in TF-A.

Henceforth, removing the weak API with a configurable macro "TWED_DELAY"
of numeric data type in generic code and simplifying the implementation.
By default "TWED_DELAY" is defined to zero, and the delay value need to
be explicitly set by the platforms during buildtime.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I25cd6f628e863dc40415ced3a82d0662fdf2d75a
2022-04-17 23:48:10 +01:00
Jorge Troncoso a8904e94f0 refactor(ufs): delete unused variables
The result variable is not being used so it's better to delete it.

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: Icae614076ce1ba7cdc86267473d59a8bec682f6c
2022-04-14 14:35:12 -07:00
Sayanta Pattanayak 70d986ddbb feat(spmc): prevent read only xlat tables with the EL3 SPMC
If using the EL3 SPMC ensure that we don't mark the translation
tables as read only. The SPMC requires the ability to map and
unmap a partitions RX/TX buffers at runtime.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ibb78a6a2e3847ce4ec74ce81a9bb61ce34fec24c
2022-04-13 09:44:52 +01:00
Marc Bonnici 1d63ae4d0d feat(spmc): enable building of the SPMC at EL3
Introduce build flag for enabling the secure partition
manager core, SPMC_AT_EL3. When enabled, the SPMC module
will be included into the BL31 image. By default the
flag is disabled.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I5ea1b953e5880a07ffc91c4dea876a375850cf2a
2022-04-13 09:44:49 +01:00
Joanna Farley 863296898a Merge "refactor(context mgmt): add cm_prepare_el3_exit_ns function" into integration 2022-04-12 17:44:52 +02:00
Joanna Farley 9c2e925964 Merge "refactor(mpam): remove initialization of EL2 registers when EL2 is used" into integration 2022-04-12 17:44:41 +02:00
Joanna Farley d2b68f498f Merge "refactor(context mgmt): refactor the cm_setup_context function" into integration 2022-04-12 17:44:31 +02:00
Joanna Farley 6cd0a2cbb3 Merge "refactor(context mgmt): remove registers accessible only from secure state from EL2 context" into integration 2022-04-12 17:44:00 +02:00
Zelalem Aweke 8b95e84870 refactor(context mgmt): add cm_prepare_el3_exit_ns function
As part of the RFC:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13651,
this patch adds the 'cm_prepare_el3_exit_ns' function. The function is
a wrapper to 'cm_prepare_el3_exit' function for Non-secure state.

When EL2 sysregs context exists (CTX_INCLUDE_EL2_REGS is
enabled) EL1 and EL2 sysreg values are restored from the context
instead of directly updating the registers.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I9b071030576bb05500d54090e2a03b3f125d1653
2022-04-12 17:42:11 +02:00
Zelalem Aweke fd5da7a847 refactor(mpam): remove initialization of EL2 registers when EL2 is used
The patch removes initialization of MPAM EL2 registers when an EL2
software exists. The patch assumes the EL2 software will perform
the necessary initializations of the registers.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I5bed81bc22f417bc3e3cbbcd860a8553cd4307cd
2022-04-12 17:41:51 +02:00
Zelalem Aweke 2bbad1d126 refactor(context mgmt): refactor the cm_setup_context function
This patch splits the function 'cm_setup_context' into four
functions to make it more readable and easier to maintain.

The function is split into the following functions based on
the security state of the context.

 - setup_context_common - performs common initializations
 - setup_secure_context - performs Secure state specific
			  initializations
 - setup_realm_context - performs Realm state specific
			 initializations
 - setup_ns_context - performs Non-secure state specific
		      initializations

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: Ie14a1c2fc6586087e7aa36537cf9064c80802f8f
2022-04-12 17:41:41 +02:00
Zelalem Aweke 7f41bcc76d refactor(context mgmt): remove registers accessible only from secure state from EL2 context
The following registers are only accessible from secure state,
therefore don't need to be saved/restored during world switch.
 - SDER32_EL2
 - VSTCR_EL2
 - VSTTBR_EL2

This patch removes these registers from EL2 context.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I24d08aacb1b6def261c7b37d3e1265bb76adafdc
2022-04-12 17:41:23 +02:00
Lauren Wehrmeister 807d6d6217 Merge "chore(measured boot): remove unused DTC flags" into integration 2022-04-12 17:19:01 +02:00
Sandrine Bailleux 2d1ba79cde Merge "style(plat/arm/corstone1000): resolve checkpatch warnings" into integration 2022-04-12 17:17:14 +02:00
Daniel Boulby a58a25e5d2 docs(build): update GCC to version 11.2-2022.02
This toolchain provides multiple cross compilers and is publicly
available on developer.arm.com.

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: Ia14de2c7d9034a6f0bc56535e961fffc81bcbf29
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2022-04-12 10:22:30 +01:00
Bipin Ravi 63446c27d1 fix(errata): workaround for Cortex-X2 erratum 2147715
Cortex-X2 erratum 2147715 is a Cat B erratum that applies to revision
r2p0 and is fixed in r2p1. The workaround is to set CPUACTLR_EL1[22]=1,
which will cause the CFP instruction to invalidate all branch predictor
resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I2d81867486d9130f2c36cd4554ca9a8f37254b57
2022-04-11 17:00:19 -05:00
Sandrine Bailleux 71e2ea8323 Merge "refactor(arm): use MBEDTLS_CONFIG_FILE macro" into integration 2022-04-11 14:33:04 +02:00
Manish V Badarkhe def5571db2 refactor(arm): use MBEDTLS_CONFIG_FILE macro
Used MBEDTLS_CONFIG_FILE macro for including mbedTLS
configuration.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I374b59a31df3ab1e69481b2c37a6f7455a106b6e
2022-04-11 14:32:59 +02:00
Sandrine Bailleux a934332d98 Merge "refactor(corstone700): namespace MHU driver filenames" into integration 2022-04-11 12:47:08 +02:00
Venkatesh Yadav Abbarapu 81333eac71 fix(xilinx): fix mismatching function prototype
The reported function raises a error when compilers assert the flag
`-Warray-parameter=`, signaling that an array-type argument was promoted
to a pointer-type argument. We observed this behaviour with the gcc 11.2
version.

plat/xilinx/common/pm_service/pm_ipi.c:263:34: error: argument 1 of type 'uint32_t *'
{aka 'unsigned int *'} declared as a pointer [-Werror=array-parameter=]
263 | uint32_t calculate_crc(uint32_t *payload, uint32_t bufsize)
      |                        ~~~~~~~~~~^~~~~~~
In file included from plat/xilinx/common/pm_service/pm_ipi.c:16:
plat/xilinx/common/include/pm_ipi.h:30:33: note: previously declared as an array 'uint32_t[8]'
{aka 'unsigned int[8]'}
   30 | uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize);
      |                        ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
cc1.real: all warnings being treated as errors

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I7329f2e76ee0ca5faba71eb50babd20a796fee64
2022-04-11 09:27:02 +05:30
Okash Khawaja 5a030ce4ae fix(bakery_lock): add __unused for clang
is_lock_acquired() function is only used in assert() statements, so when
compiling without asserts, e.g. with DEBUG=0, the function is unused.
this is okay when compiling with gcc because the function is marked as
inline but that doesn't work for clang. let's mark this as __unused to
avoid -Wunused-function warning-as-error.

Change-Id: I93f808fd15f715a65d1bd4f7592affb7997c4bad
Signed-off-by: Okash Khawaja <okash@google.com>
2022-04-08 18:17:43 +01:00
Marc Bonnici b61d94a1a2 refactor(spm_mm): reorganize secure partition manager code
In preparation for adding the EL3 SPMC configuration as defined in
the FF-A specification, restructure the existing SPM_MM code.

With this restructuring of the code, the 'spm_mm' directory is
renamed as 'spm' and the code inside has been split into two
sub-directories named 'common' and 'spm_mm'. The code in 'spm_mm'
directory contains the code that implements the MM interface.
In subsequent patches, the 'spmc' directory will be introduced
under the 'spm' directory providing the code that implements
the 'FF-A' interface.

Currently the common functionality for S-EL1 partitions is
limited to assembler functions to enter and exit an SP
synchronously.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I37739b9b53bc68e151ab5c1c0c6a15b3ee362241
2022-04-08 15:36:22 +01:00
Manish Pandey 9bd3cb5c96 Merge changes I573e6478,I52dc3bee,I7e543664 into integration
* changes:
  feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs
  feat(gic600ae_fmu): disable SMID for unavailable blocks
  feat(gic600ae_fmu): introduce support for RAS error handling
2022-04-08 14:42:45 +02:00
Sandrine Bailleux 92c356e2ed chore(measured boot): remove unused DTC flags
We no longer need to pass special flags to the device tree compiler
for measured boot. These are a left over from the days where we used
to pass BL2 measurement to BL2 image via TB_FW configuration file.

This should have been removed as part of commit eab78e9ba4
("refactor(measured_boot): remove passing of BL2 hash via device
tree") but was missed at the time.

Change-Id: Iced7e60af7ca660c342c0fc3a33b51865d67f04d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-04-08 10:33:56 +02:00
Manish Pandey 141791088e Merge "build(changelog): add new scope for TI platform" into integration 2022-04-07 17:44:31 +02:00
Varun Wadekar 6a1c17c770 feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs
The following SMIDs are disabled by default.

* GICD: MBIST REQ error and GICD FMU ClkGate override
* PPI: MBIST REQ error and PPI FMU ClkGate override
* ITS: MBIST REQ error and ITS FMU ClkGate override

This patch explicitly enables them during the FMU init sequence.

Change-Id: I573e64786e3318d4cbcd07d0a1caf25f8e6e9200
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2022-04-07 15:21:40 +02:00
Manish Pandey f6ca81ddfb Merge changes from topic "jc/detect_feat" into integration
* changes:
  docs(build): update the feature enablement flags
  refactor(el3-runtime): replace ARM_ARCH_AT_LEAST macro with FEAT flags
  refactor(el3-runtime): add arch-features detection mechanism
2022-04-07 15:19:04 +02:00
Manish Pandey fe029b5829 Merge changes from topic "mapping" into integration
* changes:
  feat(debug): update print_memory_map.py
  feat(bl_common): add XLAT tables symbols in linker script
2022-04-07 14:55:58 +02:00
Yann Gautier d16bfe0fef feat(debug): update print_memory_map.py
Add some entries in blx_symbols, that are used when the flag
SEPARATE_CODE_AND_RODATA is not enabled (__RO_* and __TEXT_RESIDENT_*).
Add all new symbols that were not yet present in the script.
Correct __BSS_END to __BSS_END__, and add __BSS_START__.
Add new *_XLAT_TABLE_* symbols.
As those strings are longer than 22, update display format string to
be dependent on the longest string.
The script also skips lines for which the _START__ and _END__
symbols have the same address (empty sections).

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I6c510ced6116b35d14ee2cb7a6711405604380d6
2022-04-07 13:46:31 +02:00
Varun Wadekar 3f0094c15d feat(gic600ae_fmu): disable SMID for unavailable blocks
This patch updates the gic600_fmu_init function to disable all safety
mechanisms for a block ID that is not present on the platform. All
safety mechanisms for GIC-600AE are enabled by default and should be
disabled for blocks that are not present on the platform to avoid
false positive RAS errors.

Change-Id: I52dc3bee9a8b49fd2e51d7ed851fdc803a48e6e3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2022-04-07 10:00:23 +02:00
Yann Gautier bb5b942e6f feat(bl_common): add XLAT tables symbols in linker script
Add __BASE_XLAT_TABLE_START__/_END__ and __XLAT_TABLE_START__/_END__
symbols in the linker script to have them in the .map file.
This allows displaying those areas when running memory map script.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I768a459c5cecc403a9b81b36a71397ecc3179f4f
2022-04-06 18:07:36 +02:00