Commit Graph

10637 Commits

Author SHA1 Message Date
Boon Khai Ng fe5637f27a fix(intel): update certificate mask for FPGA Attestation
Update the certificate mask to 0xff to cover all certificate
in Agilex family.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id40bc3aa4b3e4f7568a58581bbb03a75b0f20a0b
2022-05-11 16:57:37 +08:00
Sieu Mun Tang b703facaaa feat(intel): update to support maximum response data size
Update to support maximum (4092 bytes) response data size.
And, clean up the intel_smc_service_completed function to
directly write the response data to addr to avoid additional
copy.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I0a230e73c563d22e6999ad3473587b07382dacfe
2022-05-11 16:57:34 +08:00
Sieu Mun Tang 7e25eb8701 feat(intel): support ECDSA HASH Verification
Supporting the command to send digital signature verification
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic86f531bfe7cc7606699f2b064ac677aaf806a76
2022-05-11 16:57:31 +08:00
Sieu Mun Tang 692541051b feat(intel): support ECDSA HASH Signing
Supporting the command to send digital signature signing
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I12cf0f1ceaf07c33a110eae398d3ad82a9b13d38
2022-05-11 16:57:29 +08:00
Sieu Mun Tang 49446866a5 feat(intel): support ECDH request
This command sends the request on generating a share secret on
Diffie-Hellman key exchange.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic7c8470cf036ea8c17bf87401f49936950b3e1d6
2022-05-11 16:57:25 +08:00
Sieu Mun Tang 583050607e feat(intel): support ECDSA SHA-2 Data Signature Verification
This command support ECC based signature verification on a blob.
Supported ECC algorithm are NISP P-256, NISP P-384, Brainpool 256
and Brainpool 384.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I7f43d2a69bbe6693ec1bb90f32b817cf00f9f5ae
2022-05-11 16:57:23 +08:00
Sieu Mun Tang 07912da1b7 feat(intel): support ECDSA SHA-2 Data Signing
This command support ECC based signing on a blob. Supported ECC algorithm
are NISP P-256, NISP P-384, Brainpool 256 and Brainpool 384.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I82f95ddafa6b62f8cd882fce9a3e63e469c85067
2022-05-11 16:57:20 +08:00
Sieu Mun Tang d2fee94afa feat(intel): support ECDSA Get Public Key
To support the ECDSA feature and send the command
as a request to get the public key

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9d7bb5b6ab8ef7d4f3ceb21ff0068baf3175a1ac
2022-05-11 16:57:17 +08:00
Sieu Mun Tang 537ff05257 feat(intel): support session based SDOS encrypt and decrypt
Extends existing Secure Data Object Service (SDOS) encryption and
decryption mailbox command to include session id and context id. The
new format requires an opened crypto service session.

A separated SMC function ID is introduced for the new format and it is
only supported by Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I2627750e8337c1af66217e9cb45981a9e06e7d19
2022-05-11 16:57:13 +08:00
Sieu Mun Tang 6726390eb0 feat(intel): support AES Crypt Service
Enable Support for AES Crypt Service to send request
to encrypt or decrypt a blob. Command will send a memory
location that SDM will read and also memory location that
SDM will write back after encryption or decryption operation.
Response will be sent back after the crypto operation is done,
and data is written back to the destination

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I86ea4ff64dda2fbb1000591e30fa8cb2640ce954
2022-05-11 16:57:11 +08:00
Sieu Mun Tang c05ea29690 feat(intel): support HMAC SHA-2 MAC verify request
This command sends request on checking the integrity and authenticity
of a blob by comparing the calculated MAC with tagged MAC. The
comparison result will be returned in response.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ifefdf67f088d7612d2ec2459d71faf2ec8181222
2022-05-11 16:57:08 +08:00
Sieu Mun Tang 7e8249a2db feat(intel): support SHA-2 hash digest generation on a blob
This command is to request the SHA-2 hash digest on a blob.
If input has a key, the output shall be key-hash digest.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I08cb82d89a8e8f7bfe04f5f01e079ea49fe38cf5
2022-05-11 16:57:02 +08:00
Sieu Mun Tang 24f9dc8a43 feat(intel): support extended random number generation
The random number generation (RNG) mailbox command format
is updated to extends the support to upto 4080 bytes random
number generation. The new RNG format requires an opened
crypto service session.

A separated SMC function ID is introduced for the new RNG
format and it is only supported by Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I3f044a3c01ff7cb50be4705e2c1f982bf6f61432
2022-05-11 16:56:45 +08:00
Sieu Mun Tang 342a0618c7 feat(intel): support crypto service key operation
Support crypto service key operation mailbox commands through SMC.

Crypto service key operation begin by sending an open crypto service
session request to SDM firmware. Once successfully open the session,
send crypto service key management commands (import, export, remove
and get key info) with the associated session id to SDM firmware.
The crypto service key is required before perform any crypto service
(encryption, signing, etc). Last, close the session after finishes
crypto service. All crypto service keys associated with this session
will be erased by SDM firmware.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I02406533f38b9607eb1ec7e1395b9dc2d084a9e3
2022-05-11 10:06:41 +08:00
Sieu Mun Tang 6dc00c24ab feat(intel): support crypto service session
Support crypto service open and close session mailbox commands through
SMC.

Crypto service support begin by sending an open crypto service session
request to SDM firmware. Last, close the session after finishes crypto
service. All crypto service parameters with this session will be erased
by SDM firmware.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I48968498bbd6f2e71791f4ed38dd5f369e171082
2022-05-11 10:06:37 +08:00
Sieu Mun Tang 581182c191 feat(intel): extend attestation service to Agilex family
This patch extends the functionality of FPGA Crypto Services (FCS) to
support FPGA Attestation feature in Agilex device.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I3c2e29d2fa04d394e9f65d8143d7f4e57389cd02
2022-05-11 10:06:32 +08:00
Boon Khai Ng 49d44ec5f3 fix(intel): flush dcache before sending certificate to mailbox
Due to the cache coherency issue the dcache need to flush
before sending the certificate to the mailbox

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I39d5144519d9c7308597698b4cbea1b8aba0a849
2022-05-11 10:03:39 +08:00
Sieu Mun Tang 651841f201 fix(intel): introduce a generic response error code
This patch will introduce a generic error code (0x3ff)
to be used in case where Secure Device Manager (SDM)
mailbox request is not failing (returns OK with no error
code) but BL31 instead wants to return error/reject
to the calling software. This value aligns with generic
error code implemented in SDM for consistency.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9894c7df8897fff9aa80970940a6f3f6bfa30bb7
2022-05-11 10:03:31 +08:00
Sieu Mun Tang 4837a64093 fix(intel): allow non-secure access to FPGA Crypto Services (FCS)
Allows non-secure software to access FPGA Crypto Services (FCS)
through secure monitor calls (SMC).

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I805b3f650abf5e118e2c55e469866d5d0ca68048
2022-05-11 10:02:46 +08:00
Sieu Mun Tang 7facacec63 feat(intel): single certificate feature enablement
Extend the functionality of FPGA Crypto Service
(FCS) to support FPGA single certificate feature
so that the counter value can be updated with
only one preauthorized certificate

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibde87e4ee46367cf7f27f7bb0172838ab8766340
2022-05-11 10:01:54 +08:00
Sieu Mun Tang d17408316d feat(intel): initial commit for attestation service
This is to extend the functionality of FPGA Crypto Service (FCS)
to support FPGA Attestation feature in Stratix 10 device.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ib15783383dc9a06a2f0dc6dc1786f44b89f32cb1
2022-05-11 09:59:55 +08:00
Sieu Mun Tang 02d3ef333d fix(intel): update encryption and decryption command logic
This change is to re-align HPS cryption logic with
underlying Secure Device Manager's (SDM) mailbox API.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I8fc90982d3cddceaf401c1a112ff8e20861bf4c5
2022-05-11 09:49:25 +08:00
Bipin Ravi aeef2c22da Merge "fix(errata): workaround for Cortex-A710 erratum 2008768" into integration 2022-05-10 22:49:06 +02:00
Bipin Ravi 76d07972d6 Merge "fix(errata): workaround for Cortex-A78 erratum 2395406" into integration 2022-05-10 22:40:55 +02:00
Madhukar Pappireddy f0f631fd44 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration 2022-05-10 20:17:51 +02:00
Bipin Ravi 24cf4d70dc Merge "fix(security): report CVE 2022 23960 missing for aarch32 A57 and A72" into integration 2022-05-10 16:49:08 +02:00
Madhukar Pappireddy a11cbe7132 Merge "feat(snprintf): add support for length specifiers" into integration 2022-05-10 16:27:21 +02:00
Joanna Farley 3eb8cb4b54 Merge "fix(errata): workaround for Cortex-A78 erratum 2376745" into integration 2022-05-10 15:57:27 +02:00
Joanna Farley 926224e22e Merge "fix(amu): limit virtual offset register access to NS world" into integration 2022-05-10 15:55:05 +02:00
Olivier Deprez 3d70568089 Merge changes from topic "ffa_el3_spmc" into integration
* changes:
  feat(spmc): add helper to obtain a partitions FF-A version
  feat(spmd): enable SPMD to forward FFA_VERSION to EL3 SPMC
  feat(spmc): enable handling FFA_VERSION ABI
  feat(spmc): add helper function to obtain endpoint mailbox
  feat(spmc): add helper function to obtain hyp structure
  feat(spmc): enable parsing of messaging methods from manifest
2022-05-10 15:18:36 +02:00
Manish Pandey f41a85e9cb Merge "fix(st): add missing header include" into integration 2022-05-10 14:36:46 +02:00
Olivier Deprez 18c3320859 Merge "fix(cm): add barrier before el3 ns exit" into integration 2022-05-10 14:15:51 +02:00
Marc Bonnici c2b1434369 feat(spmc): add helper to obtain a partitions FF-A version
Add a helper function to obtain the FF-A version of a calling
partition. This is used to ensure that the SPMC maintains
backwards compatibility if the partition implements a lower
minor version for the same major version than the SPMC.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I5b364a1e510a999bb0c4cacae28f23f8a42a1e3e
2022-05-10 09:38:57 +01:00
Marc Bonnici 9576fa93a2 feat(spmd): enable SPMD to forward FFA_VERSION to EL3 SPMC
In order to allow the EL3 SPMC to know the FF-A version of the
entity running in the normal world, allow the SPMD to
forward the call rather than replying on its behalf.

This solution works as the EL3 can ERET directly back to
the calling partition however this is not an option
when the SPMC resides in a lower exception level. A new
approach will be required to support such scenario.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ic2d6e49c06340167eadefe893c6e1e20b67ab498
2022-05-10 09:36:20 +01:00
Marc Bonnici 0c7707fdf2 feat(spmc): enable handling FFA_VERSION ABI
Report the SPMC version to the caller, currently v1.1 and
also store the requested version to allow the SPMC to
use the corresponding FF-A version in future ABI calls.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I79aafd1e6694cbd4b231bbd0cac5834a71063d79
2022-05-10 09:36:20 +01:00
Marc Bonnici f16b6ee3de feat(spmc): add helper function to obtain endpoint mailbox
Add a helper function to obtain the relevant mailbox buffers
depending on which entity was last run. This will be used in
subsequent functionality to populate requested information in
the callers RX buffer.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I85959ced4d1454be05a7b3fb6853ed3ab7f0cf3e
2022-05-10 09:36:20 +01:00
Marc Bonnici a7c00505f8 feat(spmc): add helper function to obtain hyp structure
We assume that the first descriptor in the normal world
endpoints is reserved for the hypervisor and add a helper
function to enable retrieving this directly.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I67c3589994eb820ef420db6ab7e8bd0825d64455
2022-05-10 09:36:20 +01:00
Marc Bonnici 3de378ff8c feat(spmc): enable parsing of messaging methods from manifest
Ensure that the `messaging-methods` entry is populated in
an SP's manifest. Currently only direct messaging is supported
so alert if this does not match the manifest entry.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I67f1fad71a3507627993a004e0f8579388faf178
2022-05-10 09:36:15 +01:00
kadabi 701e94b08f feat(snprintf): add support for length specifiers
Add long, long long and size_t length specifiers to
snprintf similar to vprintf. This will help capturing
all the UART logs into a logbuffer and makes snprintf
functionally equivalent to vprintf.

Change-Id: Ib9bd20e2b040c9b8755cf7ed7c9b4da555604810
Signed-off-by: Channagoud kadabi <kadabi@google.com>
2022-05-10 01:01:12 +02:00
John Powell 3b577ed53d fix(errata): workaround for Cortex-A78 erratum 2395406
Cortex-A78 erratum 2395406 is a cat B erratum that applies to revisions
r0p0 - r1p2 and is still open. The workaround is to set bit[40] of
CPUACTLR2 which will disable folding of demand requests into older
prefetches with L2 miss requests outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If06f988f05f925c2a4bed3e6a9414b6acdfec894
2022-05-10 00:04:24 +02:00
johpow01 af220ebbe4 fix(errata): workaround for Cortex-A710 erratum 2008768
Cortex-A710 erratum 2008768 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to clear
the ED bit in each ERXCTLR_EL1 register before setting the PWRDN bit in
CPUPWRCTLR_EL1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib2171c06da762dd4155b02c03d86766f1616381d
2022-05-09 20:02:10 +02:00
John Powell 5d796b3a25 fix(errata): workaround for Cortex-A78 erratum 2376745
Cortex-A78 erratum 2376745 is a cat B erratum that applies to revisions
r0p0 - r1p2 and is still open. The workaround is to set bit[0] of
CPUACTLR2 which will force PLDW/PFRM ST to behave like PLD/PRFM LD and
not cause invalidation to other PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I6f1a3a7d613c5ed182a7028f912e0f6ae3aa7f98
2022-05-09 19:09:22 +02:00
Olivier Deprez 04825031b2 fix(cm): add barrier before el3 ns exit
In cm_prepare_el3_exit_ns, SCR_EL3.NS bit change (to non-secure) is not
committed before the EL2 restoration sequence happens.
At ICC_SRE_EL2 write in cm_el2_sysregs_context_restore, NS is still 0
from CPU perspective (with EEL2=0) which is an invalid condition and
triggers a fault. By adding ISB, SCR_EL3 gets synced with NS=1/EEL2=0
before ICC_SRE_EL2 write.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie72a6152aa7729e66b3344c1b7b0749f54cafb6f
2022-05-09 17:41:29 +02:00
Manish Pandey c3bdd3d3cf Merge changes Idfd268cd,I362445b9,Ibea052d3,I28cb8f74,I501ae76a, ... into integration
* changes:
  feat(imx8mp): enable BL32 fdt overlay support on imx8mp
  feat(imx8mq): enable optee fdt overlay support
  feat(imx8mn): enable optee fdt overlay support
  feat(imx8mm): enable optee fdt overlay support
  feat(imx8mp): add trusty for imx8mp
  feat(imx8mq): enable trusty for imx8mq
  feat(imx8mn): enable Trusty OS for imx8mn
  feat(imx8mm): enable Trusty OS on imx8mm
  feat(imx8/imx8m): switch to xlat_tables_v2
  feat(imx8m): enable the coram_s tz by default on imx8mn/mp
  feat(imx8m): enable the csu init on imx8m
  feat(imx8m): add a simple csu driver for imx8m family
  refactor(imx8m): replace magic number with enum type
  feat(imx8m): add imx csu/rdc enum type defines for imx8m
  fix(imx8m): check the validation of domain id
  feat(imx8m): enable conditional build for SDEI
2022-05-09 11:30:50 +02:00
Manish Pandey 42f31f5f10 Merge "feat(plat/imx8m): do not release JR0 to NS if HAB is using it" into integration 2022-05-09 10:40:00 +02:00
Jacky Bai aeff14640a feat(imx8mp): enable BL32 fdt overlay support on imx8mp
Allow OP-TEE to generate a device-tree overlay binary
that will be applied by u-boot on the regular dtb.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Idfd268cdd8b7ba321f8e1b9b85c2bba7ffdeddf0
2022-05-07 17:33:58 +08:00
Silvano di Ninno 023750c6a8 feat(imx8mq): enable optee fdt overlay support
Enable optee fdt overlay support

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I362445b93dc293a27c99b0d20a73f6b06ad0cd39
2022-05-07 17:33:58 +08:00
Silvano di Ninno 2612891288 feat(imx8mn): enable optee fdt overlay support
Enable optee fdt overlay support.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ibea052d35bf746475b8618b3a879eea80875333c
2022-05-07 17:33:58 +08:00
Silvano di Ninno 9d0eed111c feat(imx8mm): enable optee fdt overlay support
Enable optee fdt overlay support.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I28cb8f744236868727ef4a09d7d2946070404d4d
2022-05-07 17:33:58 +08:00
Jacky Bai 8b9c21b480 feat(imx8mp): add trusty for imx8mp
Add trusty support on i.MX8MP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I501ae76ac35b8c059b3f0a9ce1d51ed13cbdbfe2
2022-05-07 17:33:58 +08:00