Commit Graph

427 Commits

Author SHA1 Message Date
davidcunado-arm 1ae5c8bbde Merge pull request #879 from Summer-ARM/sq/mt-support
ARM platforms: Add support for MT bit in MPIDR
2017-03-28 18:15:20 +01:00
Summer Qin d8d6cf247b ARM platforms: Add support for MT bit in MPIDR
This patch modifies some of the functions in ARM platform layer to cater
for the case when multi-threading `MT` is set in MPIDR. A new build flag
`ARM_PLAT_MT` is added, and when enabled, the functions accessing MPIDR
now assume that the `MT` bit is set for the platform and access the bit
fields accordingly.

Also, a new API plat_arm_get_cpu_pe_count is added when `ARM_PLAT_MT` is
enabled, returning the PE count within the physical cpu corresponding to
`mpidr`.

Change-Id: I04ccf212ac3054a60882761f4087bae299af13cb
Signed-off-by: Summer Qin <summer.qin@arm.com>
2017-03-27 14:53:43 +01:00
davidcunado-arm 02accf9883 Merge pull request #872 from dp-arm/dp/fix-typo
firmware-design: Fix typo in ToC header flags specification
2017-03-24 22:53:50 +00:00
dp-arm d34f4f846b firmware-design: Fix typo in ToC header flags specification
Fixes ARM-software/tf-issues#463

Change-Id: I73e0c5fbd87004953df8b1fa19319ad562ecc867
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-03-20 13:43:52 +00:00
Andre Przywara b75dc0e41c Add workaround for ARM Cortex-A53 erratum 855873
ARM erratum 855873 applies to all Cortex-A53 CPUs.
The recommended workaround is to promote "data cache clean"
instructions to "data cache clean and invalidate" instructions.
For core revisions of r0p3 and later this can be done by setting a bit
in the CPUACTLR_EL1 register, so that hardware takes care of the promotion.
As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3,
we set the bit in firmware.
Also we dump this register upon crashing to provide more debug
information.

Enable the workaround for the Juno boards.

Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2017-03-20 10:57:46 +00:00
davidcunado-arm 510a9de79f Merge pull request #860 from jeenu-arm/hw-asstd-coh
Patches for platforms with hardware-assisted coherency
2017-03-17 12:34:37 +00:00
davidcunado-arm 28ee754d15 Merge pull request #856 from antonio-nino-diaz-arm/an/dynamic-xlat
Introduce version 2 of the translation tables library
2017-03-16 12:42:32 +00:00
Antonio Nino Diaz ccbec91c0c Apply workaround for errata 813419 of Cortex-A57
TLBI instructions for EL3 won't have the desired effect under specific
circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and
TLBI twice each time.

Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.

This errata has been enabled for Juno.

The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.

Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-03-08 14:40:27 +00:00
Antonio Nino Diaz 0b64f4ef43 Add dynamic region support to xlat tables lib v2
Added APIs to add and remove regions to the translation tables
dynamically while the MMU is enabled. Only static regions are allowed
to overlap other static ones (for backwards compatibility).

A new private attribute (MT_DYNAMIC / MT_STATIC) has been added to
flag each region as such.

The dynamic mapping functionality can be enabled or disabled when
compiling by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1
or 0. This can be done per-image.

TLB maintenance code during dynamic table mapping and unmapping has
also been added.

Fixes ARM-software/tf-issues#310

Change-Id: I19e8992005c4292297a382824394490c5387aa3b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-03-08 14:40:27 +00:00
danh-arm 6feeb0814d Merge pull request #859 from Summer-ARM/sq/update-doc
Update LOAD_IMAGE_V2 user guide documentation
2017-03-02 17:03:12 +00:00
davidcunado-arm bea7caff8d Merge pull request #853 from vwadekar/tegra-changes-from-downstream-v3
Tegra changes from downstream v3
2017-03-02 15:27:33 +00:00
Jeenu Viswambharan b0408e87f7 PSCI: Optimize call paths if all participants are cache-coherent
The current PSCI implementation can apply certain optimizations upon the
assumption that all PSCI participants are cache-coherent.

  - Skip performing cache maintenance during power-up.

  - Skip performing cache maintenance during power-down:

    At present, on the power-down path, CPU driver disables caches and
    MMU, and performs cache maintenance in preparation for powering down
    the CPU. This means that PSCI must perform additional cache
    maintenance on the extant stack for correct functioning.

    If all participating CPUs are cache-coherent, CPU driver would
    neither disable MMU nor perform cache maintenance. The CPU being
    powered down, therefore, remain cache-coherent throughout all PSCI
    call paths. This in turn means that PSCI cache maintenance
    operations are not required during power down.

  - Choose spin locks instead of bakery locks:

    The current PSCI implementation must synchronize both cache-coherent
    and non-cache-coherent participants. Mutual exclusion primitives are
    not guaranteed to function on non-coherent memory. For this reason,
    the current PSCI implementation had to resort to bakery locks.

    If all participants are cache-coherent, the implementation can
    enable MMU and data caches early, and substitute bakery locks for
    spin locks. Spin locks make use of architectural mutual exclusion
    primitives, and are lighter and faster.

The optimizations are applied when HW_ASSISTED_COHERENCY build option is
enabled, as it's expected that all PSCI participants are cache-coherent
in those systems.

Change-Id: Iac51c3ed318ea7e2120f6b6a46fd2db2eae46ede
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-03-02 11:00:20 +00:00
Jeenu Viswambharan 3c251af392 build: Define build option for hardware-assisted coherency
The boolean build option HW_ASSISTED_COHERENCY is introduced to enable
various optimizations in ARM Trusted Software, when built for such
systems. It's set to 0 by default.

Change-Id: I638390da6e1718fe024dcf5b402e07084f1eb014
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-03-02 11:00:20 +00:00
Summer Qin 7334e5c739 Update LOAD_IMAGE_V2 user guide documentation
Now the TRUSTED_BOARD_BOOT is supported for AArch64 when LOAD_IMAGE_V2
is enabled. This patch updates the user-guide.md documentation for the
same.

Change-Id: I97de07435c81258c2a5f41a30a69736863a10bd1
Signed-off-by: Summer Qin <summer.qin@arm.com>
2017-03-02 10:23:09 +00:00
Varun Wadekar 018b84803d Tegra: enable ECC/Parity protection for Cortex-A57 CPUs
This patch enables L2 ECC and Parity Protection for ARM Cortex-A57 CPUs
for Tegra SoCs.

Change-Id: I038fcd529991d0201a4951ce2730ab71b1c980f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-02-28 08:50:01 -08:00
danh-arm c1a29754e1 Merge pull request #848 from douglas-raillard-arm/dr/improve_errata_doc
Clarify errata ERRATA_A53_836870 documentation
2017-02-28 12:07:32 +00:00
Douglas Raillard 3fbe46d73f Clarify errata ERRATA_A53_836870 documentation
The errata is enabled by default on r0p4, which is confusing given that
we state we do not enable errata by default.

This patch clarifies this sentence by saying it is enabled in hardware
by default.

Change-Id: I70a062d93e1da2416d5f6d5776a77a659da737aa
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-02-23 16:15:05 +00:00
Varun Wadekar e10842167b Tegra: init normal/crash console for platforms
The BL2 fills in the UART controller ID to be used as the normal as
well as the crash console on Tegra platforms. The controller ID to
UART controller base address mapping is handled by each Tegra SoC
the base addresses might change across Tegra chips.

This patch adds the handler to parse the platform params to get the
UART ID for the per-soc handlers.

Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-02-22 09:16:34 -08:00
Varun Wadekar e0d4158c71 Tegra: add tzdram_base to plat_params_from_bl2 struct
This patch adds another member, tzdram_base, to the plat_params_from_bl2 struct
in order to store the TZDRAM carveout base address used to load the Trusted OS.
The monitor programs the memory controller with the TZDRAM base and size in order
to deny any accesses from the NS world.

Change-Id: If39b8674d548175d7ccb6525c18d196ae8a8506c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-02-22 09:16:34 -08:00
danh-arm 8da12f612e Merge pull request #843 from jeenu-arm/cas-lock
Introduce locking primitives using CAS instruction
2017-02-20 13:59:50 +00:00
davidcunado-arm 108e4df7f1 Merge pull request #834 from douglas-raillard-arm/dr/use_dc_zva_zeroing
Use DC ZVA instruction to zero memory
2017-02-16 14:49:37 +00:00
davidcunado-arm 78e9e18f52 Merge pull request #838 from davidcunado-arm/dc/update_userguide
Migrate to Linaro Release 16.12
2017-02-16 09:56:45 +00:00
Jeenu Viswambharan c877b41487 Introduce locking primitives using CAS instruction
The ARMv8v.1 architecture extension has introduced support for far
atomics, which includes compare-and-swap. Compare and Swap instruction
is only available for AArch64.

Introduce build options to choose the architecture versions to target
ARM Trusted Firmware:

  - ARM_ARCH_MAJOR: selects the major version of target ARM
    Architecture. Default value is 8.

  - ARM_ARCH_MINOR: selects the minor version of target ARM
    Architecture. Default value is 0.

When:

  (ARM_ARCH_MAJOR > 8) || ((ARM_ARCH_MAJOR == 8) && (ARM_ARCH_MINOR >= 1)),

for AArch64, Compare and Swap instruction is used to implement spin
locks. Otherwise, the implementation falls back to using
load-/store-exclusive instructions.

Update user guide, and introduce a section in Firmware Design guide to
summarize support for features introduced in ARMv8 Architecture
Extensions.

Change-Id: I73096a0039502f7aef9ec6ab3ae36680da033f16
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-02-14 09:26:11 +00:00
David Cunado e361cf3b51 Migrate to Linaro Release 16.12
This Linaro release updates both the binaries and the toolchain:
Linaro binaries upgraded 16.06 --> 16.12
AArch64 compiler upgraded 15.05 (gcc 4.9) --> 5.3-2015.05 (gcc 5.3)
AArch32 compiler upgraded 15.05 (gcc 4.9) --> 5.3-2015.05 (gcc 5.3)

The ARM TF codebase has been tested against these new binaries. This patch
updates the User Guide to reflect that the 16.12 release is now a supported
Linaro Release.

Change-Id: I6247e820f591df7d05df4f622ee45a3abf2c2d72
Signed-off-by: David Cunado <david.cunado@arm.com>
2017-02-13 17:26:24 +00:00
davidcunado-arm fd6d90d8a6 Merge pull request #826 from dp-arm/dp/psci-stat-abstraction
Decouple PSCI stat residency calculation from PMF
2017-02-13 17:21:03 +00:00
dp-arm 04c1db1e57 PSCI: Decouple PSCI stat residency calculation from PMF
This patch introduces the following three platform interfaces:

* void plat_psci_stat_accounting_start(const psci_power_state_t *state_info)

  This is an optional hook that platforms can implement in order
  to perform accounting before entering a low power state.  This
  typically involves capturing a timestamp.

* void plat_psci_stat_accounting_stop(const psci_power_state_t *state_info)

  This is an optional hook that platforms can implement in order
  to perform accounting after exiting from a low power state.  This
  typically involves capturing a timestamp.

* u_register_t plat_psci_stat_get_residency(unsigned int lvl,
	const psci_power_state_t *state_info,
	unsigned int last_cpu_index)

  This is an optional hook that platforms can implement in order
  to calculate the PSCI stat residency.

If any of these interfaces are overridden by the platform, it is
recommended that all of them are.

By default `ENABLE_PSCI_STAT` is disabled.  If `ENABLE_PSCI_STAT`
is set but `ENABLE_PMF` is not set then an alternative PSCI stat
collection backend must be provided.  If both are set, then default
weak definitions of these functions are provided, using PMF to
calculate the residency.

NOTE: Previously, platforms did not have to explicitly set
`ENABLE_PMF` since this was automatically done by the top-level
Makefile.

Change-Id: I17b47804dea68c77bc284df15ee1ccd66bc4b79b
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-02-13 14:33:06 +00:00
David Cunado dbd1ab8e90 Update AEM and Cortex Models versions
AEMv8-A Model release v8.2 has been made available and Trusted Firmware
has been tested against these versions as part of its CI system. This
patch updates the user guide documentation to reflect the version of AEM
and Cortex Models that Trusted Firmware has been tested against.

Also, the Linaro Release Notes link was broken and this patch updates the
link.

Change-Id: I88729cef909a69fff629036f480fd6168ad7dc9a
Signed-off-by: David Cunado <david.cunado@arm.com>
2017-02-10 15:28:16 +00:00
Douglas Raillard 308d359b26 Introduce unified API to zero memory
Introduce zeromem_dczva function on AArch64 that can handle unaligned
addresses and make use of DC ZVA instruction to zero a whole block at a
time. This zeroing takes place directly in the cache to speed it up
without doing external memory access.

Remove the zeromem16 function on AArch64 and replace it with an alias to
zeromem. This zeromem16 function is now deprecated.

Remove the 16-bytes alignment constraint on __BSS_START__ in
firmware-design.md as it is now not mandatory anymore (it used to comply
with zeromem16 requirements).

Change the 16-bytes alignment constraints in SP min's linker script to a
8-bytes alignment constraint as the AArch32 zeromem implementation is now
more efficient on 8-bytes aligned addresses.

Introduce zero_normalmem and zeromem helpers in platform agnostic header
that are implemented this way:
* AArch32:
	* zero_normalmem: zero using usual data access
	* zeromem: alias for zero_normalmem
* AArch64:
	* zero_normalmem: zero normal memory  using DC ZVA instruction
	                  (needs MMU enabled)
	* zeromem: zero using usual data access

Usage guidelines: in most cases, zero_normalmem should be preferred.

There are 2 scenarios where zeromem (or memset) must be used instead:
* Code that must run with MMU disabled (which means all memory is
  considered device memory for data accesses).
* Code that fills device memory with null bytes.

Optionally, the following rule can be applied if performance is
important:
* Code zeroing small areas (few bytes) that are not secrets should use
  memset to take advantage of compiler optimizations.

  Note: Code zeroing security-related critical information should use
  zero_normalmem/zeromem instead of memset to avoid removal by
  compilers' optimizations in some cases or misbehaving versions of GCC.

Fixes ARM-software/tf-issues#408

Change-Id: Iafd9663fc1070413c3e1904e54091cf60effaa82
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-02-06 17:01:39 +00:00
Masahiro Yamada 4fff02c629 zynqmp: remove RESET_TO_BL31=1 from build instruction
RESET_TO_BL31=1 is specified by plat/xilinx/zynqmp/platform.mk with
"override" directive.  So, RESET_TO_BL31=1 is guaranteed without any
operation on users' side.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-06 17:59:58 +09:00
danh-arm bcc2bf0977 Merge pull request #821 from jeenu-arm/errata-printing
Errata printing infrastructure
2017-01-31 15:40:20 +00:00
Jeenu Viswambharan 10bcd76157 Report errata workaround status to console
The errata reporting policy is as follows:

  - If an errata workaround is enabled:

    - If it applies (i.e. the CPU is affected by the errata), an INFO
      message is printed, confirming that the errata workaround has been
      applied.

    - If it does not apply, a VERBOSE message is printed, confirming
      that the errata workaround has been skipped.

  - If an errata workaround is not enabled, but would have applied had
    it been, a WARN message is printed, alerting that errata workaround
    is missing.

The CPU errata messages are printed by both BL1 (primary CPU only) and
runtime firmware on debug builds, once for each CPU/errata combination.

Relevant output from Juno r1 console when ARM Trusted Firmware is built
with PLAT=juno LOG_LEVEL=50 DEBUG=1:

  VERBOSE: BL1: cortex_a57: errata workaround for 806969 was not applied
  VERBOSE: BL1: cortex_a57: errata workaround for 813420 was not applied
  INFO:    BL1: cortex_a57: errata workaround for disable_ldnp_overread was applied
  WARNING: BL1: cortex_a57: errata workaround for 826974 was missing!
  WARNING: BL1: cortex_a57: errata workaround for 826977 was missing!
  WARNING: BL1: cortex_a57: errata workaround for 828024 was missing!
  WARNING: BL1: cortex_a57: errata workaround for 829520 was missing!
  WARNING: BL1: cortex_a57: errata workaround for 833471 was missing!
  ...
  VERBOSE: BL31: cortex_a57: errata workaround for 806969 was not applied
  VERBOSE: BL31: cortex_a57: errata workaround for 813420 was not applied
  INFO:    BL31: cortex_a57: errata workaround for disable_ldnp_overread was applied
  WARNING: BL31: cortex_a57: errata workaround for 826974 was missing!
  WARNING: BL31: cortex_a57: errata workaround for 826977 was missing!
  WARNING: BL31: cortex_a57: errata workaround for 828024 was missing!
  WARNING: BL31: cortex_a57: errata workaround for 829520 was missing!
  WARNING: BL31: cortex_a57: errata workaround for 833471 was missing!
  ...
  VERBOSE: BL31: cortex_a53: errata workaround for 826319 was not applied
  INFO:    BL31: cortex_a53: errata workaround for disable_non_temporal_hint was applied

Also update documentation.

Change-Id: Iccf059d3348adb876ca121cdf5207bdbbacf2aba
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-01-30 14:53:19 +00:00
Jeenu Viswambharan 186cbd0815 user-guide.md: Fix FVP references
The current user guide mentions that Foundation model doesn't support
debugger interface. Clarify that all FVPs support --cadi-server option
such that a CADI-compliant debugger can connect to and control model
execution.

Also fix broken URL to FVP home page.

Change-Id: Ia14d618a4e0abb4b228eb1616040f9b51fb3f6f9
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-01-26 14:20:22 +00:00
danh-arm 67748e4827 Merge pull request #788 from jeenu-arm/cpuops-framework
Add provision to extend CPU operations at more levels
2016-12-20 12:27:58 +00:00
Sandrine Bailleux 34ba298e09 Improve FWU documentation
- Clarify the documentation of the 'FWU_SMC_IMAGE_COPY' SMC in the
   Firmware Update guide. Also extend the list of pre-conditions to
   include the additional input validation implemented by previous
   patches.

 - Improve documentation of bl1_plat_mem_check() in the porting
   guide. It now specifies that the generic FWU code protects
   bl1_plat_mem_check() from integer overflows resulting from
   the addition of the base address and size passed in arguments.

Change-Id: I07b47a3778df7b9c089529b2dd2135707640a91c
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2016-12-20 11:43:10 +00:00
Dan Handley 19d2595d41 Merge pull request #785 from dp-arm/dp/nvcounter 2016-12-20 11:36:54 +00:00
danh-arm 78b4c5b078 Merge pull request #778 from antonio-nino-diaz-arm/an/xlat-fixes
Fixes and improvements to translation tables library
2016-12-19 15:39:01 +00:00
David Cunado 8434f76ff4 Update Foundation Model version
Foundation Model release 10.2 has been made available and Trusted
Firmware has been tested against that it as part of its CI system.

This patch updates the user guide documentation to reflect the version
of Foundation Model that Trusted Firmware has been tested against.

Change-Id: I8571e1027b24892b41d04b93b24245a371ca2cae
Signed-off-by: David Cunado <david.cunado@arm.com>
2016-12-15 15:53:50 +00:00
Jeenu Viswambharan 5dd9dbb5bf Add provision to extend CPU operations at more levels
Various CPU drivers in ARM Trusted Firmware register functions to handle
power-down operations. At present, separate functions are registered to
power down individual cores and clusters.

This scheme operates on the basis of core and cluster, and doesn't cater
for extending the hierarchy for power-down operations. For example,
future CPUs might support multiple threads which might need powering
down individually.

This patch therefore reworks the CPU operations framework to allow for
registering power down handlers on specific level basis. Henceforth:

  - Generic code invokes CPU power down operations by the level
    required.

  - CPU drivers explicitly mention CPU_NO_RESET_FUNC when the CPU has no
    reset function.

  - CPU drivers register power down handlers as a list: a mandatory
    handler for level 0, and optional handlers for higher levels.

All existing CPU drivers are adapted to the new CPU operations framework
without needing any functional changes within.

Also update firmware design guide.

Change-Id: I1826842d37a9e60a9e85fdcee7b4b8f6bc1ad043
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2016-12-15 15:41:40 +00:00
dp-arm d35dee23b6 tbbr: Fix updating of Non-Trusted NV counter
The previous code required that a certificate be signed with the ROT
key before the platform's NV counter could be updated with the value
in the certificate.  This implies that the Non-Trusted NV counter was
not being updated for Non-Trusted content certificates, as they cannot
be signed with the ROT key in the TBBR CoT scheme.

The code is reworked to only allow updating the platform's Trusted NV
counter when a certificate protected by the Trusted NV counter is
signed with the ROT key.

Content certificates protected by the Non-Trusted NV counter are
allowed to update the platform's Non-Trusted NV counter, assuming
that the certificate value is higher than the platform's value.

A new optional platform API has been introduced, named
plat_set_nv_ctr2().  Platforms may choose to implement it and perform
additional checks based on the authentication image descriptor before
modifying the NV counters.  A default weak implementation is available
that just calls into plat_set_nv_ctr().

Fixes ARM-software/tf-issues#426

Change-Id: I4fc978fd28a3007bc0cef972ff1f69ad0413b79c
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2016-12-15 14:12:35 +00:00
Antonio Nino Diaz 0029624fe2 Add PLAT_xxx_ADDR_SPACE_SIZE definitions
Added the definitions `PLAT_PHY_ADDR_SPACE_SIZE` and
`PLAT_VIRT_ADDR_SPACE_SIZE` which specify respectively the physical
and virtual address space size a platform can use.

`ADDR_SPACE_SIZE` is now deprecated. To maintain compatibility, if any
of the previous defines aren't present, the value of `ADDR_SPACE_SIZE`
will be used instead.

For AArch64, register ID_AA64MMFR0_EL1 is checked to calculate the
max PA supported by the hardware and to verify that the previously
mentioned definition is valid. For AArch32, a 40 bit physical
address space is considered.

Added asserts to check for overflows.

Porting guide updated.

Change-Id: Ie8ce1da5967993f0c94dbd4eb9841fc03d5ef8d6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2016-12-13 15:35:15 +00:00
Jeenu Viswambharan adefa3d82f Docs: Fix monospace formatting in user guide
Change-Id: I28b2790ff2f87b9fe3cf1020e59e1e0a00be6f97
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2016-12-13 13:38:00 +00:00
danh-arm 5c0df525ac Merge pull request #762 from douglas-raillard-arm/dr/doc_build_info
Clarify dependency for PSCI_EXTENDED_STATE_ID
2016-11-22 10:49:57 +00:00
danh-arm 52ec41ab30 Merge pull request #755 from vwadekar/trusty-spd
spd: dispatcher for interacting with the Trusty TEE
2016-11-22 10:47:34 +00:00
Douglas Raillard 91a422d69f Clarify dependency for PSCI_EXTENDED_STATE_ID
Add dependency information in the user guide for ARM_RECOM_STATE_ID_ENC
that needs to be set when using PSCI_EXTENDED_STATE_ID on ARM
platforms. Also clarify the build error message.

Change-Id: Id125a0299b179f5f222bca4e2503204bf89a3c59
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2016-11-22 10:05:47 +00:00
danh-arm 18c7c2df6c Merge pull request #758 from douglas-raillard-arm/dr/doc_interrupt_handler
Docs: Clarify IRQ/FIQ handler API in Interrupt Design Guide
2016-11-21 16:38:11 +00:00
Douglas Raillard 94a8ca24cb Docs: Clarify IRQ/FIQ handler API in Interrupt Design Guide
The API description currently states that interrupt handlers
(interrupt_type_handler_t pointers) SHOULD return a pointer
to the target cpu_context.

This patch rewords the description of the interrupts handlers to state
that it MUST return a pointer to the target security context. It also
warns about potential portability issue. Specifically, this pointer is
not used on AArch64 and calls to context library APIs must be used to
ask BL31 to return to a specific context. However, this could change in
the future and interrupt handlers must always return the pointer.

Change-Id: I3f82a046de4d7a5b51a8cbebe7eb2a00dbbdb4f0
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2016-11-17 10:04:49 +00:00
danh-arm 686019d206 Merge pull request #757 from douglas-raillard-arm/dr/doc_plat_psci_ops
Document plat_psci_ops.(system_off|system_reset)
2016-11-16 11:36:01 +00:00
Douglas Raillard b3fa89ad45 firmware-design.md: Fix broken link
Fix a link broken by a missing space that turned
it into a link to an non-existent anchor.

Change-Id: Ie863e963db28afa3a28b69d3f63bd7638bdf5af9
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2016-11-14 16:04:01 +00:00
Douglas Raillard 7dd570eff5 Document plat_psci_ops.(system_off|system_reset)
fixes ARM-Software/tf-issues#346

Change-Id: I946c8eab650bba7407775462ce91f394d767e079
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2016-11-14 11:44:11 +00:00
Varun Wadekar 948c090d8c spd: dispatcher for interacting with the Trusty TEE
This patch adds the secure payload dispatcher for interacting
with Google's Trusty TEE. Documentation for Trusty can be found
at https://source.android.com/security/trusty

Original authors:
-----------------
* Arve Hjønnevåg <arve@android.com>
* Michael Ryleev <gmar@google.com>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2016-11-08 15:50:04 -08:00