At the moment BL31 dynamically discovers the CPU topology of an FPGA system at runtime, but does not export it to the non-secure world. Any BL33 user would typically looks at the devicetree to learn about existing CPUs. This patch exports a minimum /cpus node in a devicetree to satisfy the binding. This means that no cpumaps or caches are described. This could be added later if needed. An existing /cpus node in the DT will make the code bail out with a message. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I589a2b3412411a3660134bdcef3a65e8200e1d7e |
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a5ds | ||
arm_fpga | ||
common | ||
corstone700 | ||
fvp | ||
fvp_ve | ||
juno | ||
n1sdp | ||
rddaniel | ||
rddanielxlr | ||
rde1edge | ||
rdn1edge | ||
sgi575 | ||
sgm775 | ||
tc0 |