Sieu Mun Tang 24f9dc8a43 feat(intel): support extended random number generation ... The random number generation (RNG) mailbox command format is updated to extends the support to upto 4080 bytes random number generation. The new RNG format requires an opened crypto service session. A separated SMC function ID is introduced for the new RNG format and it is only supported by Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I3f044a3c01ff7cb50be4705e2c1f982bf6f61432		2022-05-11 16:56:45 +08:00
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aarch64	feat(intel): add macro to switch between different UART PORT	2022-04-05 14:25:30 +08:00
drivers	feat(intel): enable firewall for OCRAM in BL31	2022-04-28 19:08:35 +08:00
include	feat(intel): support extended random number generation	2022-05-11 16:56:45 +08:00
sip	feat(intel): support extended random number generation	2022-05-11 16:56:45 +08:00
soc	fix(intel): allow non-secure access to FPGA Crypto Services (FCS)	2022-05-11 10:02:46 +08:00
bl2_plat_mem_params_desc.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00
socfpga_delay_timer.c	feat(intel): implement timer init divider via cpu frequency. (#1)	2022-05-06 17:37:45 +02:00
socfpga_image_load.c	intel: Implement platform specific system reset 2	2019-12-30 10:17:04 +08:00
socfpga_psci.c	fix(intel): fix ECC Double Bit Error handling	2022-03-09 09:14:16 +08:00
socfpga_sip_svc.c	feat(intel): support extended random number generation	2022-05-11 16:56:45 +08:00
socfpga_storage.c	intel: Refactor common platform code [2/5]	2019-11-28 12:47:58 +08:00
socfpga_topology.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00