Mustafa Yigit Bilgen 322b00fcfb Tegra186: clean CPU wake times from L2 cache ... When entering C7, ATF disables caches and flushes the L1 cache. However, wake_time[cpu] can still remain in the L2 cache, causing later reads to it to fetch from DRAM. This will read stale values. Fix this by aligning wake_time[cpu] to cache lines, and explicitly cleaning it before disabling caches. Change-Id: Id73d095b479677595a6b3dd0abb240a1fef5f311 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2017-04-05 14:09:51 -07:00
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t132	Tegra: GIC: enable FIQ interrupt handling	2017-02-28 08:50:01 -08:00
t186	Tegra186: clean CPU wake times from L2 cache	2017-04-05 14:09:51 -07:00
t210	plat/tegra: Enable Cortex-A53 erratum 855873 workaround	2017-03-20 10:57:50 +00:00