Mustafa Yigit Bilgen 322b00fcfb Tegra186: clean CPU wake times from L2 cache ... When entering C7, ATF disables caches and flushes the L1 cache. However, wake_time[cpu] can still remain in the L2 cache, causing later reads to it to fetch from DRAM. This will read stale values. Fix this by aligning wake_time[cpu] to cache lines, and explicitly cleaning it before disabling caches. Change-Id: Id73d095b479677595a6b3dd0abb240a1fef5f311 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2017-04-05 14:09:51 -07:00
..
drivers	Tegra186: update t18x_ari.h to v3.0	2017-04-05 14:09:51 -07:00
plat_psci_handlers.c	Tegra186: clean CPU wake times from L2 cache	2017-04-05 14:09:51 -07:00
plat_secondary.c	Tegra186: save/restore BL31 context to/from TZDRAM	2017-03-23 14:17:32 -07:00
plat_setup.c	Tegra186: use helper functions to get major/minor version	2017-03-30 16:49:05 -07:00
plat_sip_calls.c	Tegra186: Add smc handler for coresight clock gating	2017-04-05 13:56:36 -07:00
plat_trampoline.S	Tegra186: trampoline: update "System Suspend" exit criteria	2017-04-05 13:56:41 -07:00
platform_t186.mk	Tegra186: handlers to get BL31 arguments from previous bootloader	2017-03-30 16:49:05 -07:00