BenjaminLimJL f65bdf3a54 feat(intel): implement timer init divider via cpu frequency. (#1) ... Get cpu frequency and update the timer init div with it. The timer is vary based on the cpu frequency instead of hardcoded. The implementation shall apply to only Agilex and S10 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422		2022-05-06 17:37:45 +02:00
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aarch64	feat(intel): add macro to switch between different UART PORT	2022-04-05 14:25:30 +08:00
drivers	feat(intel): enable firewall for OCRAM in BL31	2022-04-28 19:08:35 +08:00
include	feat(intel): implement timer init divider via cpu frequency. (#1)	2022-05-06 17:37:45 +02:00
sip	fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS)	2022-04-30 09:24:03 +08:00
soc	feat(intel): add SMC support for HWMON voltage and temp sensor	2022-04-28 22:46:56 +08:00
bl2_plat_mem_params_desc.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00
socfpga_delay_timer.c	feat(intel): implement timer init divider via cpu frequency. (#1)	2022-05-06 17:37:45 +02:00
socfpga_image_load.c	intel: Implement platform specific system reset 2	2019-12-30 10:17:04 +08:00
socfpga_psci.c	fix(intel): fix ECC Double Bit Error handling	2022-03-09 09:14:16 +08:00
socfpga_sip_svc.c	feat(intel): add SMC support for HWMON voltage and temp sensor	2022-04-28 22:46:56 +08:00
socfpga_storage.c	intel: Refactor common platform code [2/5]	2019-11-28 12:47:58 +08:00
socfpga_topology.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00