Caesar Wang 4ea8dc4e02 rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5 ... The default value of L2CTLR_DATA_RAM_LATENCY is 2, depends to the test result on rk3399, the A72 will need lower voltage for high frequency if it's set to be 5, and almost no effect on performance. Change-Id: I99a6a43edcc0c58f7775c10f4b85669dc3eff66d Signed-off-by: Caesar Wang <wxt@rock-chips.com>		2016-10-25 03:32:31 +08:00
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arm	Introduce ARM SiP service	2016-10-12 15:36:45 +01:00
common	AArch32: Common changes needed for BL1/BL2	2016-09-21 16:27:15 +01:00
compat	AArch32: Add essential ARM platform and FVP support	2016-08-10 18:01:38 +01:00
mediatek	Remove MT6795 plat_sip_svc.c to fix Coverity analysis error.	2016-09-19 14:20:42 +08:00
nvidia/tegra	Migrate platform makefile to new console driver location	2016-08-09 17:33:57 +01:00
qemu	Migrate platform makefile to new console driver location	2016-08-09 17:33:57 +01:00
rockchip	rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5	2016-10-25 03:32:31 +08:00
xilinx/zynqmp	zynqmp: Make MMIO write FW call synchronous	2016-09-13 09:19:03 -07:00