Caesar Wang 4d5d98c77c rockchip: fixes the clock select and divide register for rk3399 ... As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON register. As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the CRU_CLKSEL_CON offset is 0x100,not 0x80. Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529		2016-09-29 00:51:19 +08:00
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drivers	rockchip: fixes the clock select and divide register for rk3399	2016-09-29 00:51:19 +08:00
include	Merge pull request #654 from rockchip-linux/rk3399-suspend-resume	2016-07-18 16:18:37 +01:00
plat_sip_calls.c	rockchip: SIP call use 32 bit return value for rk3399	2016-09-10 06:37:08 +08:00
platform.mk	Merge pull request #684 from rockchip-linux/add-sdram-for-rk3399	2016-08-25 13:56:25 +01:00
rk3399_def.h	rockchip: rk3399: add dram driver	2016-08-25 08:37:42 +08:00