arm-trusted-firmware/plat/intel/soc/common
Sieu Mun Tang 52ed157fd6 fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS)
This patch is to add size checking to make sure that
each certificate and encryption/decryption request
are 4-byte align as this driver is expecting. Unaligned
size may indicate invalid/corrupted request hence will
be rejected.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ib6f97849ec470e45679c5adc4fbfa3afd10eda90
2022-04-30 09:24:03 +08:00
..
aarch64 feat(intel): add macro to switch between different UART PORT 2022-04-05 14:25:30 +08:00
drivers feat(intel): enable firewall for OCRAM in BL31 2022-04-28 19:08:35 +08:00
include feat(intel): add SMC support for HWMON voltage and temp sensor 2022-04-28 22:46:56 +08:00
sip fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS) 2022-04-30 09:24:03 +08:00
soc feat(intel): add SMC support for HWMON voltage and temp sensor 2022-04-28 22:46:56 +08:00
bl2_plat_mem_params_desc.c intel: Platform common code refactor 2019-08-01 16:39:27 +08:00
socfpga_delay_timer.c plat: intel: Additional instruction required to enable global timer 2020-06-08 22:03:54 +00:00
socfpga_image_load.c intel: Implement platform specific system reset 2 2019-12-30 10:17:04 +08:00
socfpga_psci.c fix(intel): fix ECC Double Bit Error handling 2022-03-09 09:14:16 +08:00
socfpga_sip_svc.c feat(intel): add SMC support for HWMON voltage and temp sensor 2022-04-28 22:46:56 +08:00
socfpga_storage.c intel: Refactor common platform code [2/5] 2019-11-28 12:47:58 +08:00
socfpga_topology.c intel: Platform common code refactor 2019-08-01 16:39:27 +08:00