arm-trusted-firmware/include/bl31
Achin Gupta b44a4435c9 Add S-EL1 interrupt handling support in the TSPD
This patch adds support in the TSPD for registering a handler for
S-EL1 interrupts. This handler ferries the interrupts generated in the
non-secure state to the TSP at 'tsp_fiq_entry'. Support has been added
to the smc handler to resume execution in the non-secure state once
interrupt handling has been completed by the TSP.

There is also support for resuming execution in the normal world if
the TSP receives a EL3 interrupt. This code is currently unused.

Change-Id: I816732595a2635e299572965179f11aa0bf93b69
2014-05-22 17:54:46 +01:00
..
services Reduce deep nesting of header files 2014-05-06 13:57:48 +01:00
bl31.h Rework memory information passing to BL3-x images 2014-05-22 16:19:32 +01:00
context.h Merge pull request #78 from jeenuv:tf-issues-148 2014-05-19 12:54:05 +01:00
context_mgmt.h Add context library API to change a bit in SCR_EL3 2014-05-22 17:45:59 +01:00
interrupt_mgmt.h Introduce interrupt registration framework in BL3-1 2014-05-22 17:46:56 +01:00
runtime_svc.h Add S-EL1 interrupt handling support in the TSPD 2014-05-22 17:54:46 +01:00