Xing Zheng ae7a93521f rockchip: rk3399: sperate the BL31 parameters for sharing ... Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE and TZRAM_SIZE for DDR secure regions), we can split them and don't have to hardcode the range in two places. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>		2017-02-24 20:07:44 +08:00
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drivers	rockchip: rk3399: configure the DDR secure region for BL31 image	2017-02-24 20:07:44 +08:00
include	rockchip: rk3399: sperate the BL31 parameters for sharing	2017-02-24 20:07:44 +08:00
plat_sip_calls.c	rk3399: dram: use PMU M0 to do ddr frequency scaling	2017-02-24 20:07:44 +08:00
platform.mk	rk3399: dram: use PMU M0 to do ddr frequency scaling	2017-02-24 20:07:44 +08:00
rk3399_def.h	rockchip: Clean up header and referenced files	2017-02-24 20:07:44 +08:00