2019-11-11 11:11:06 +00:00
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#
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2020-08-20 18:48:09 +01:00
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# Copyright (c) 2020, Arm Limited. All rights reserved.
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2019-11-11 11:11:06 +00:00
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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2020-01-24 15:02:27 +00:00
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include lib/libfdt/libfdt.mk
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2019-11-11 11:11:06 +00:00
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RESET_TO_BL31 := 1
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ifeq (${RESET_TO_BL31}, 0)
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$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
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endif
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2019-12-16 14:08:27 +00:00
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ifeq (${ENABLE_PIE}, 1)
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override SEPARATE_CODE_AND_RODATA := 1
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endif
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2019-11-11 11:11:06 +00:00
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CTX_INCLUDE_AARCH32_REGS := 0
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ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
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$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
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endif
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ifeq (${TRUSTED_BOARD_BOOT}, 1)
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$(error "TRUSTED_BOARD_BOOT must be disabled")
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endif
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2020-07-08 13:01:00 +01:00
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PRELOADED_BL33_BASE := 0x80080000
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2019-11-11 11:11:06 +00:00
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2020-07-08 13:01:00 +01:00
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FPGA_PRELOADED_DTB_BASE := 0x80070000
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2019-11-11 11:11:06 +00:00
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$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
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2020-07-07 10:40:46 +01:00
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FPGA_PRELOADED_CMD_LINE := 0x1000
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$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE))
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2019-11-11 11:11:06 +00:00
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# Treating this as a memory-constrained port for now
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USE_COHERENT_MEM := 0
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2020-01-15 10:20:09 +00:00
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# This can be overridden depending on CPU(s) used in the FPGA image
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2019-11-11 11:11:06 +00:00
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HW_ASSISTED_COHERENCY := 1
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2020-04-09 10:10:09 +01:00
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PL011_GENERIC_UART := 1
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2020-08-20 18:48:09 +01:00
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SUPPORT_UNKNOWN_MPID ?= 1
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2020-01-15 10:20:09 +00:00
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FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
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# select a different set of CPU files, depending on whether we compile for
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# hardware assisted coherency cores or not
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ifeq (${HW_ASSISTED_COHERENCY}, 0)
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# Cores used without DSU
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FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/cortex_a73.S
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else
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# AArch64-only cores
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FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
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lib/cpus/aarch64/cortex_a76ae.S \
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lib/cpus/aarch64/cortex_a77.S \
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2020-06-01 22:49:34 +01:00
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lib/cpus/aarch64/cortex_a78.S \
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2020-01-15 10:20:09 +00:00
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lib/cpus/aarch64/neoverse_n1.S \
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lib/cpus/aarch64/neoverse_e1.S \
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2020-09-30 21:28:03 +01:00
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lib/cpus/aarch64/neoverse_v1.S \
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2020-09-30 21:34:51 +01:00
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lib/cpus/aarch64/cortex_a78_ae.S \
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2020-01-15 10:20:09 +00:00
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lib/cpus/aarch64/cortex_a65.S \
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2020-06-25 13:10:38 +01:00
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lib/cpus/aarch64/cortex_a65ae.S \
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lib/cpus/aarch64/cortex_klein.S \
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lib/cpus/aarch64/cortex_matterhorn.S
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2020-01-15 10:20:09 +00:00
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# AArch64/AArch32 cores
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FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
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lib/cpus/aarch64/cortex_a75.S
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endif
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2019-11-11 11:11:06 +00:00
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2020-08-20 18:48:09 +01:00
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ifeq (${SUPPORT_UNKNOWN_MPID}, 1)
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# Add support for unknown/invalid MPIDs (aarch64 only)
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$(eval $(call add_define,SUPPORT_UNKNOWN_MPID))
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FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S
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endif
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2020-03-25 15:50:38 +00:00
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# Allow detection of GIC-600
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GICV3_SUPPORT_GIC600 := 1
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2020-04-03 18:59:20 +01:00
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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FPGA_GIC_SOURCES := ${GICV3_SOURCES} \
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2019-12-03 14:08:21 +00:00
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plat/common/plat_gicv3.c \
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plat/arm/board/arm_fpga/fpga_gicv3.c
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2019-11-11 11:11:06 +00:00
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arm_fpga: Add devicetree file
The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.
Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.
Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-08-03 12:54:58 +01:00
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FDT_SOURCES := fdts/arm_fpga.dts
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2019-11-11 11:11:06 +00:00
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PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
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PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
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2020-01-24 15:02:27 +00:00
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BL31_SOURCES += common/fdt_wrappers.c \
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2020-06-04 19:01:48 +01:00
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common/fdt_fixup.c \
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2020-01-24 15:02:27 +00:00
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drivers/delay_timer/delay_timer.c \
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2019-11-11 11:11:06 +00:00
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drivers/delay_timer/generic_delay_timer.c \
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drivers/arm/pl011/${ARCH}/pl011_console.S \
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plat/common/plat_psci_common.c \
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plat/arm/board/arm_fpga/fpga_pm.c \
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plat/arm/board/arm_fpga/fpga_topology.c \
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plat/arm/board/arm_fpga/fpga_console.c \
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plat/arm/board/arm_fpga/fpga_bl31_setup.c \
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${FPGA_CPU_LIBS} \
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${FPGA_GIC_SOURCES}
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2020-08-03 13:06:38 +01:00
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$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,31))
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arm_fpga: Add post-build linker script
For the Arm Ltd. FPGAs to run, we need to load several payloads into the
FPGA's memory:
- Some trampoline code at address 0x0, to jump to BL31's entry point.
- The actual BL31 binary at the beginning of DRAM.
- The (generic) DTB image to describe the hardware.
- The actual non-secure payloads (kernel, ramdisks, ...)
The latter is application specific, but the first three blobs are rather
generic.
Since the uploader tool supports ELF binaries, it seems helpful to
combine these three images into one .axf file, as this also simplifies
the command line.
Add a post-build linker script, that combines those three bits into one
ELF file, together with their specific load addresses.
Include a call to "ld" with this linker script in the platform Makefile,
so it will be build automatically. The result will be called "bl31.axf".
Change-Id: I4a90da16fa1e0e83b51d19e5b1daf61f5a0bbfca
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-16 17:13:33 +01:00
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$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,31))
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2020-08-03 13:06:38 +01:00
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arm_fpga: Add post-build linker script
For the Arm Ltd. FPGAs to run, we need to load several payloads into the
FPGA's memory:
- Some trampoline code at address 0x0, to jump to BL31's entry point.
- The actual BL31 binary at the beginning of DRAM.
- The (generic) DTB image to describe the hardware.
- The actual non-secure payloads (kernel, ramdisks, ...)
The latter is application specific, but the first three blobs are rather
generic.
Since the uploader tool supports ELF binaries, it seems helpful to
combine these three images into one .axf file, as this also simplifies
the command line.
Add a post-build linker script, that combines those three bits into one
ELF file, together with their specific load addresses.
Include a call to "ld" with this linker script in the platform Makefile,
so it will be build automatically. The result will be called "bl31.axf".
Change-Id: I4a90da16fa1e0e83b51d19e5b1daf61f5a0bbfca
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-16 17:13:33 +01:00
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bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/build_axf.ld
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$(ECHO) " LD $@"
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$(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -o ${BUILD_PLAT}/bl31.axf
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all: bl31.axf
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