2019-11-11 11:11:06 +00:00
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/utils_def.h>
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#ifndef FPGA_DEF_H
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#define FPGA_DEF_H
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/*
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2019-12-16 14:08:27 +00:00
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* These are set to large values to account for images describing systems with
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* larger cluster configurations.
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*
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* For cases where the number of clusters, cores or threads is smaller than a
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* maximum value below, this does not affect the PSCI functionality as any PEs
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* that are present will still be indexed appropriately regardless of any empty
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* entries in the array used to represent the topology.
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2019-11-11 11:11:06 +00:00
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*/
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2020-05-13 14:09:58 +01:00
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2020-06-25 13:10:38 +01:00
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#define FPGA_MAX_CLUSTER_COUNT 4
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2019-12-16 14:08:27 +00:00
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#define FPGA_MAX_CPUS_PER_CLUSTER 8
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#define FPGA_MAX_PE_PER_CPU 4
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2019-11-11 11:11:06 +00:00
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#define FPGA_PRIMARY_CPU 0x0
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/*******************************************************************************
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* FPGA image memory map related constants
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******************************************************************************/
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2020-04-09 10:25:43 +01:00
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/*
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* UART base address, just for the crash console, as a fallback.
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* The actual console UART address is taken from the DT.
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*/
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#define PLAT_FPGA_CRASH_UART_BASE 0x7ff80000
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2019-11-11 11:11:06 +00:00
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2020-01-24 15:02:27 +00:00
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#define FPGA_DEFAULT_TIMER_FREQUENCY 10000000
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2019-12-02 13:33:40 +00:00
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2019-11-11 11:11:06 +00:00
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#endif
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