2015-03-19 18:58:55 +00:00
|
|
|
/*
|
2022-01-08 23:08:02 +00:00
|
|
|
* Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
|
2015-03-19 18:58:55 +00:00
|
|
|
*
|
2017-05-03 09:38:09 +01:00
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
2015-03-19 18:58:55 +00:00
|
|
|
*/
|
|
|
|
|
2018-12-14 00:18:21 +00:00
|
|
|
#include <assert.h>
|
|
|
|
|
|
|
|
#include <platform_def.h>
|
|
|
|
|
2015-03-19 18:58:55 +00:00
|
|
|
#include <arch.h>
|
2018-12-14 00:18:21 +00:00
|
|
|
#include <bl1/bl1.h>
|
|
|
|
#include <common/bl_common.h>
|
2019-10-17 14:46:51 +01:00
|
|
|
#include <lib/fconf/fconf.h>
|
2020-06-11 22:32:11 +01:00
|
|
|
#include <lib/fconf/fconf_dyn_cfg_getter.h>
|
2018-12-14 00:18:21 +00:00
|
|
|
#include <lib/utils.h>
|
|
|
|
#include <lib/xlat_tables/xlat_tables_compat.h>
|
2019-01-25 14:30:04 +00:00
|
|
|
#include <plat/arm/common/plat_arm.h>
|
2018-12-14 00:18:21 +00:00
|
|
|
#include <plat/common/platform.h>
|
|
|
|
|
2015-03-19 18:58:55 +00:00
|
|
|
/* Weak definitions may be overridden in specific ARM standard platform */
|
|
|
|
#pragma weak bl1_early_platform_setup
|
|
|
|
#pragma weak bl1_plat_arch_setup
|
|
|
|
#pragma weak bl1_plat_sec_mem_layout
|
2021-01-27 19:08:47 +00:00
|
|
|
#pragma weak arm_bl1_early_platform_setup
|
2016-11-14 12:01:04 +00:00
|
|
|
#pragma weak bl1_plat_prepare_exit
|
2018-09-03 17:41:13 +01:00
|
|
|
#pragma weak bl1_plat_get_next_image_id
|
|
|
|
#pragma weak plat_arm_bl1_fwu_needed
|
2021-01-27 19:08:47 +00:00
|
|
|
#pragma weak arm_bl1_plat_arch_setup
|
2021-03-03 20:19:38 +00:00
|
|
|
#pragma weak arm_bl1_platform_setup
|
2015-03-19 18:58:55 +00:00
|
|
|
|
2018-07-06 16:54:44 +01:00
|
|
|
#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
|
|
|
|
bl1_tzram_layout.total_base, \
|
|
|
|
bl1_tzram_layout.total_size, \
|
2021-07-13 04:33:55 +01:00
|
|
|
MT_MEMORY | MT_RW | EL3_PAS)
|
2018-07-16 14:09:15 +01:00
|
|
|
/*
|
|
|
|
* If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
|
|
|
|
* otherwise one region is defined containing both
|
|
|
|
*/
|
|
|
|
#if SEPARATE_CODE_AND_RODATA
|
|
|
|
#define MAP_BL1_RO MAP_REGION_FLAT( \
|
2018-07-06 16:54:44 +01:00
|
|
|
BL_CODE_BASE, \
|
|
|
|
BL1_CODE_END - BL_CODE_BASE, \
|
2021-07-13 04:33:55 +01:00
|
|
|
MT_CODE | EL3_PAS), \
|
2018-07-16 14:09:15 +01:00
|
|
|
MAP_REGION_FLAT( \
|
2018-07-06 16:54:44 +01:00
|
|
|
BL1_RO_DATA_BASE, \
|
|
|
|
BL1_RO_DATA_END \
|
|
|
|
- BL_RO_DATA_BASE, \
|
2021-07-13 04:33:55 +01:00
|
|
|
MT_RO_DATA | EL3_PAS)
|
2018-07-16 14:09:15 +01:00
|
|
|
#else
|
|
|
|
#define MAP_BL1_RO MAP_REGION_FLAT( \
|
|
|
|
BL_CODE_BASE, \
|
|
|
|
BL1_CODE_END - BL_CODE_BASE, \
|
2021-07-13 04:33:55 +01:00
|
|
|
MT_CODE | EL3_PAS)
|
2018-07-16 14:09:15 +01:00
|
|
|
#endif
|
2015-03-19 18:58:55 +00:00
|
|
|
|
|
|
|
/* Data structure which holds the extents of the trusted SRAM for BL1*/
|
|
|
|
static meminfo_t bl1_tzram_layout;
|
|
|
|
|
2020-07-14 11:28:36 +01:00
|
|
|
/* Boolean variable to hold condition whether firmware update needed or not */
|
|
|
|
static bool is_fwu_needed;
|
|
|
|
|
2018-07-11 11:44:22 +01:00
|
|
|
struct meminfo *bl1_plat_sec_mem_layout(void)
|
2015-03-19 18:58:55 +00:00
|
|
|
{
|
|
|
|
return &bl1_tzram_layout;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* BL1 specific platform actions shared between ARM standard platforms.
|
|
|
|
******************************************************************************/
|
|
|
|
void arm_bl1_early_platform_setup(void)
|
|
|
|
{
|
|
|
|
|
2015-10-06 14:01:35 +01:00
|
|
|
#if !ARM_DISABLE_TRUSTED_WDOG
|
|
|
|
/* Enable watchdog */
|
2019-04-16 06:59:14 +01:00
|
|
|
plat_arm_secure_wdt_start();
|
2015-10-06 14:01:35 +01:00
|
|
|
#endif
|
|
|
|
|
2015-03-19 18:58:55 +00:00
|
|
|
/* Initialize the console to provide early debug support */
|
2018-06-19 09:29:36 +01:00
|
|
|
arm_console_boot_init();
|
2015-03-19 18:58:55 +00:00
|
|
|
|
|
|
|
/* Allow BL1 to see the whole Trusted RAM */
|
|
|
|
bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
|
|
|
|
bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
void bl1_early_platform_setup(void)
|
|
|
|
{
|
|
|
|
arm_bl1_early_platform_setup();
|
|
|
|
|
|
|
|
/*
|
2016-02-15 11:54:14 +00:00
|
|
|
* Initialize Interconnect for this cluster during cold boot.
|
2015-03-19 18:58:55 +00:00
|
|
|
* No need for locks as no other CPU is active.
|
|
|
|
*/
|
2016-02-15 11:54:14 +00:00
|
|
|
plat_arm_interconnect_init();
|
2015-03-19 18:58:55 +00:00
|
|
|
/*
|
2016-02-15 11:54:14 +00:00
|
|
|
* Enable Interconnect coherency for the primary CPU's cluster.
|
2015-03-19 18:58:55 +00:00
|
|
|
*/
|
2016-02-15 11:54:14 +00:00
|
|
|
plat_arm_interconnect_enter_coherency();
|
2015-03-19 18:58:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************************
|
|
|
|
* Perform the very early platform specific architecture setup shared between
|
|
|
|
* ARM standard platforms. This only does basic initialization. Later
|
|
|
|
* architectural setup (bl1_arch_setup()) does not do anything platform
|
|
|
|
* specific.
|
|
|
|
*****************************************************************************/
|
|
|
|
void arm_bl1_plat_arch_setup(void)
|
|
|
|
{
|
2018-09-18 11:42:42 +01:00
|
|
|
#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
|
|
|
|
/*
|
|
|
|
* Ensure ARM platforms don't use coherent memory in BL1 unless
|
|
|
|
* cryptocell integration is enabled.
|
|
|
|
*/
|
2018-07-06 16:54:44 +01:00
|
|
|
assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
|
2015-03-19 18:58:55 +00:00
|
|
|
#endif
|
2018-07-06 16:54:44 +01:00
|
|
|
|
|
|
|
const mmap_region_t bl_regions[] = {
|
|
|
|
MAP_BL1_TOTAL,
|
2018-07-16 14:09:15 +01:00
|
|
|
MAP_BL1_RO,
|
2018-05-23 09:27:06 +01:00
|
|
|
#if USE_ROMLIB
|
|
|
|
ARM_MAP_ROMLIB_CODE,
|
|
|
|
ARM_MAP_ROMLIB_DATA,
|
2018-09-18 11:42:42 +01:00
|
|
|
#endif
|
|
|
|
#if ARM_CRYPTOCELL_INTEG
|
|
|
|
ARM_MAP_BL_COHERENT_RAM,
|
|
|
|
#endif
|
2018-07-06 16:54:44 +01:00
|
|
|
{0}
|
|
|
|
};
|
|
|
|
|
2018-10-19 16:44:18 +01:00
|
|
|
setup_page_tables(bl_regions, plat_arm_get_mmap());
|
2019-07-09 22:02:43 +01:00
|
|
|
#ifdef __aarch64__
|
2016-05-18 16:11:47 +01:00
|
|
|
enable_mmu_el3(0);
|
2019-07-09 22:02:43 +01:00
|
|
|
#else
|
|
|
|
enable_mmu_svc_mon(0);
|
|
|
|
#endif /* __aarch64__ */
|
2018-05-23 09:27:06 +01:00
|
|
|
|
|
|
|
arm_setup_romlib();
|
2015-03-19 18:58:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void bl1_plat_arch_setup(void)
|
|
|
|
{
|
|
|
|
arm_bl1_plat_arch_setup();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Perform the platform specific architecture setup shared between
|
|
|
|
* ARM standard platforms.
|
|
|
|
*/
|
|
|
|
void arm_bl1_platform_setup(void)
|
|
|
|
{
|
2020-06-11 22:32:11 +01:00
|
|
|
const struct dyn_cfg_dtb_info_t *fw_config_info;
|
|
|
|
image_desc_t *desc;
|
|
|
|
uint32_t fw_config_max_size;
|
|
|
|
int err = -1;
|
|
|
|
|
2015-03-19 18:58:55 +00:00
|
|
|
/* Initialise the IO layer and register platform IO devices */
|
|
|
|
plat_arm_io_setup();
|
2019-10-17 14:46:51 +01:00
|
|
|
|
2020-06-11 22:32:11 +01:00
|
|
|
/* Check if we need FWU before further processing */
|
2020-07-14 11:28:36 +01:00
|
|
|
is_fwu_needed = plat_arm_bl1_fwu_needed();
|
|
|
|
if (is_fwu_needed) {
|
2020-06-11 22:32:11 +01:00
|
|
|
ERROR("Skip platform setup as FWU detected\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set global DTB info for fixed fw_config information */
|
|
|
|
fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
|
2022-04-21 22:53:43 +01:00
|
|
|
set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
|
2020-06-11 22:32:11 +01:00
|
|
|
|
|
|
|
/* Fill the device tree information struct with the info from the config dtb */
|
|
|
|
err = fconf_load_config(FW_CONFIG_ID);
|
|
|
|
if (err < 0) {
|
|
|
|
ERROR("Loading of FW_CONFIG failed %d\n", err);
|
|
|
|
plat_error_handler(err);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
|
|
|
|
* is successful then load TB_FW_CONFIG device tree.
|
|
|
|
*/
|
|
|
|
fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
|
|
|
|
if (fw_config_info != NULL) {
|
|
|
|
err = fconf_populate_dtb_registry(fw_config_info->config_addr);
|
|
|
|
if (err < 0) {
|
|
|
|
ERROR("Parsing of FW_CONFIG failed %d\n", err);
|
|
|
|
plat_error_handler(err);
|
|
|
|
}
|
|
|
|
/* load TB_FW_CONFIG */
|
|
|
|
err = fconf_load_config(TB_FW_CONFIG_ID);
|
|
|
|
if (err < 0) {
|
|
|
|
ERROR("Loading of TB_FW_CONFIG failed %d\n", err);
|
|
|
|
plat_error_handler(err);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ERROR("Invalid FW_CONFIG address\n");
|
|
|
|
plat_error_handler(err);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
|
|
|
|
desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
|
|
|
|
assert(desc != NULL);
|
|
|
|
desc->ep_info.args.arg0 = fw_config_info->config_addr;
|
2019-10-17 14:46:51 +01:00
|
|
|
|
2022-01-08 23:08:02 +00:00
|
|
|
#if CRYPTO_SUPPORT
|
2018-07-30 13:41:52 +01:00
|
|
|
/* Share the Mbed TLS heap info with other images */
|
|
|
|
arm_bl1_set_mbedtls_heap();
|
2022-01-08 23:08:02 +00:00
|
|
|
#endif /* CRYPTO_SUPPORT */
|
2018-09-25 11:37:23 +01:00
|
|
|
|
2018-06-11 16:40:36 +01:00
|
|
|
/*
|
|
|
|
* Allow access to the System counter timer module and program
|
|
|
|
* counter frequency for non secure images during FWU
|
|
|
|
*/
|
2018-11-30 15:43:56 +00:00
|
|
|
#ifdef ARM_SYS_TIMCTL_BASE
|
2018-06-11 16:40:36 +01:00
|
|
|
arm_configure_sys_timer();
|
2018-11-30 15:43:56 +00:00
|
|
|
#endif
|
2018-12-12 17:14:29 +00:00
|
|
|
#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
|
2018-06-11 16:40:36 +01:00
|
|
|
write_cntfrq_el0(plat_get_syscnt_freq2());
|
2018-12-12 17:14:29 +00:00
|
|
|
#endif
|
2015-03-19 18:58:55 +00:00
|
|
|
}
|
|
|
|
|
2015-11-26 16:31:34 +00:00
|
|
|
void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
|
|
|
|
{
|
2015-10-06 14:01:35 +01:00
|
|
|
#if !ARM_DISABLE_TRUSTED_WDOG
|
|
|
|
/* Disable watchdog before leaving BL1 */
|
2019-04-16 06:59:14 +01:00
|
|
|
plat_arm_secure_wdt_stop();
|
2015-10-06 14:01:35 +01:00
|
|
|
#endif
|
|
|
|
|
2015-11-26 16:31:34 +00:00
|
|
|
#ifdef EL3_PAYLOAD_BASE
|
|
|
|
/*
|
|
|
|
* Program the EL3 payload's entry point address into the CPUs mailbox
|
|
|
|
* in order to release secondary CPUs from their holding pen and make
|
|
|
|
* them jump there.
|
|
|
|
*/
|
2018-06-18 13:01:06 +01:00
|
|
|
plat_arm_program_trusted_mailbox(ep_info->pc);
|
2015-11-26 16:31:34 +00:00
|
|
|
dsbsy();
|
|
|
|
sev();
|
|
|
|
#endif
|
|
|
|
}
|
2018-03-07 11:32:04 +00:00
|
|
|
|
2018-09-03 17:41:13 +01:00
|
|
|
/*
|
|
|
|
* On Arm platforms, the FWU process is triggered when the FIP image has
|
|
|
|
* been tampered with.
|
|
|
|
*/
|
2020-01-29 11:42:31 +00:00
|
|
|
bool plat_arm_bl1_fwu_needed(void)
|
2018-09-03 17:41:13 +01:00
|
|
|
{
|
2020-01-29 11:42:31 +00:00
|
|
|
return !arm_io_is_toc_valid();
|
2018-09-03 17:41:13 +01:00
|
|
|
}
|
|
|
|
|
2018-03-07 11:32:04 +00:00
|
|
|
/*******************************************************************************
|
|
|
|
* The following function checks if Firmware update is needed,
|
|
|
|
* by checking if TOC in FIP image is valid or not.
|
|
|
|
******************************************************************************/
|
|
|
|
unsigned int bl1_plat_get_next_image_id(void)
|
|
|
|
{
|
2020-07-14 11:28:36 +01:00
|
|
|
return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
|
2018-03-07 11:32:04 +00:00
|
|
|
}
|