2013-10-25 09:08:21 +01:00
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/*
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2016-02-15 11:54:14 +00:00
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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2013-10-25 09:08:21 +01:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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2015-03-19 19:17:53 +00:00
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#include <arm_config.h>
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#include <arm_def.h>
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2016-03-24 10:12:42 +00:00
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#include <ccn.h>
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2014-04-09 13:13:04 +01:00
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#include <debug.h>
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2015-11-03 14:18:34 +00:00
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#include <gicv2.h>
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2014-04-09 13:14:54 +01:00
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#include <mmio.h>
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2015-03-19 19:17:53 +00:00
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#include <plat_arm.h>
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#include <v2m_def.h>
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2014-05-14 17:44:19 +01:00
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#include "../fvp_def.h"
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2013-10-25 09:08:21 +01:00
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2015-11-03 14:18:34 +00:00
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/* Defines for GIC Driver build time selection */
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#define FVP_GICV2 1
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#define FVP_GICV3 2
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#define FVP_GICV3_LEGACY 3
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2013-10-25 09:08:21 +01:00
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/*******************************************************************************
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2015-03-19 19:17:53 +00:00
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* arm_config holds the characteristics of the differences between the three FVP
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* platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
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2016-02-15 11:54:14 +00:00
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* at each boot stage by the primary before enabling the MMU (to allow
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* interconnect configuration) & used thereafter. Each BL will have its own copy
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* to allow independent operation.
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2013-10-25 09:08:21 +01:00
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******************************************************************************/
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2015-03-19 19:17:53 +00:00
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arm_config_t arm_config;
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2014-09-03 17:48:44 +01:00
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#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
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DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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2015-04-14 12:49:03 +01:00
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#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
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DEVICE2_SIZE, \
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2016-05-20 14:14:16 +01:00
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MT_DEVICE | MT_RW | MT_SECURE)
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2015-04-14 12:49:03 +01:00
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2014-02-26 16:27:53 +00:00
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/*
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2016-05-18 16:11:47 +01:00
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* Table of memory regions for various BL stages to map using the MMU.
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* This doesn't include Trusted SRAM as arm_setup_page_tables() already
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* takes care of mapping it.
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2016-06-14 17:01:00 +01:00
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*
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* The flash needs to be mapped as writable in order to erase the FIP's Table of
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* Contents in case of unrecoverable error (see plat_error_handler()).
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2014-02-26 16:27:53 +00:00
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*/
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2014-09-03 17:48:44 +01:00
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#if IMAGE_BL1
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2015-03-19 19:17:53 +00:00
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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2015-10-06 14:01:35 +01:00
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V2M_MAP_FLASH0_RW,
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2015-03-19 19:17:53 +00:00
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V2M_MAP_IOFPGA,
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2014-09-03 17:48:44 +01:00
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MAP_DEVICE0,
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MAP_DEVICE1,
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2015-04-14 12:49:03 +01:00
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MAP_DEVICE2,
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2015-10-11 14:14:55 +01:00
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#if TRUSTED_BOARD_BOOT
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ARM_MAP_NS_DRAM1,
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#endif
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2014-09-03 17:48:44 +01:00
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{0}
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};
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#endif
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#if IMAGE_BL2
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2015-03-19 19:17:53 +00:00
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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2015-10-06 14:01:35 +01:00
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V2M_MAP_FLASH0_RW,
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2015-03-19 19:17:53 +00:00
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V2M_MAP_IOFPGA,
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2014-09-03 17:48:44 +01:00
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MAP_DEVICE0,
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MAP_DEVICE1,
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2015-04-14 12:49:03 +01:00
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MAP_DEVICE2,
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2015-03-19 19:17:53 +00:00
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ARM_MAP_NS_DRAM1,
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ARM_MAP_TSP_SEC_MEM,
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2016-03-07 03:02:57 +00:00
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#if ARM_BL31_IN_DRAM
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ARM_MAP_BL31_SEC_DRAM,
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#endif
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2014-09-03 17:48:44 +01:00
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{0}
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};
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#endif
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2015-10-14 15:28:11 +01:00
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#if IMAGE_BL2U
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const mmap_region_t plat_arm_mmap[] = {
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MAP_DEVICE0,
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V2M_MAP_IOFPGA,
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{0}
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};
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#endif
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2014-09-03 17:48:44 +01:00
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#if IMAGE_BL31
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2015-03-19 19:17:53 +00:00
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_IOFPGA,
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2014-09-03 17:48:44 +01:00
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MAP_DEVICE0,
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MAP_DEVICE1,
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{0}
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};
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#endif
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#if IMAGE_BL32
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2015-03-19 19:17:53 +00:00
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const mmap_region_t plat_arm_mmap[] = {
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2016-07-11 14:13:56 +01:00
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#ifdef AARCH32
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ARM_MAP_SHARED_RAM,
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#endif
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2015-03-19 19:17:53 +00:00
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V2M_MAP_IOFPGA,
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2014-09-03 17:48:44 +01:00
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MAP_DEVICE0,
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MAP_DEVICE1,
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2014-02-26 16:27:53 +00:00
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{0}
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};
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2014-09-03 17:48:44 +01:00
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#endif
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2014-02-26 16:27:53 +00:00
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2015-03-19 19:17:53 +00:00
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ARM_CASSERT_MMAP
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2015-01-22 11:22:22 +00:00
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2015-03-19 19:17:53 +00:00
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2013-10-25 09:08:21 +01:00
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/*******************************************************************************
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* A single boot loader stack is expected to work on both the Foundation FVP
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* models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
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* SYS_ID register provides a mechanism for detecting the differences between
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* these platforms. This information is stored in a per-BL array to allow the
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* code to take the correct path.Per BL platform configuration.
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******************************************************************************/
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2015-03-19 19:17:53 +00:00
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void fvp_config_setup(void)
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2013-10-25 09:08:21 +01:00
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{
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2014-08-14 12:49:05 +01:00
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unsigned int rev, hbi, bld, arch, sys_id;
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2013-10-25 09:08:21 +01:00
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2015-03-19 19:17:53 +00:00
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sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
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rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
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hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
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bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
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arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
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2013-10-25 09:08:21 +01:00
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2014-06-26 14:27:26 +01:00
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if (arch != ARCH_MODEL) {
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ERROR("This firmware is for FVP models\n");
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2014-02-10 14:24:36 +00:00
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panic();
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2014-06-26 14:27:26 +01:00
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}
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2013-10-25 09:08:21 +01:00
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/*
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* The build field in the SYS_ID tells which variant of the GIC
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* memory is implemented by the model.
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*/
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switch (bld) {
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case BLD_GIC_VE_MMAP:
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2016-01-13 17:06:00 +00:00
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ERROR("Legacy Versatile Express memory map for GIC peripheral"
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" is not supported\n");
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2015-11-03 14:18:34 +00:00
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panic();
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2013-10-25 09:08:21 +01:00
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break;
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case BLD_GIC_A53A57_MMAP:
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break;
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default:
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2014-06-26 14:27:26 +01:00
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ERROR("Unsupported board build %x\n", bld);
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panic();
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2013-10-25 09:08:21 +01:00
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}
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/*
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* The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
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* for the Foundation FVP.
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*/
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switch (hbi) {
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2015-03-19 19:17:53 +00:00
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case HBI_FOUNDATION_FVP:
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arm_config.flags = 0;
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2014-06-26 14:27:26 +01:00
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/*
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* Check for supported revisions of Foundation FVP
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* Allow future revisions to run but emit warning diagnostic
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*/
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switch (rev) {
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2015-03-19 19:17:53 +00:00
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case REV_FOUNDATION_FVP_V2_0:
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case REV_FOUNDATION_FVP_V2_1:
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case REV_FOUNDATION_FVP_v9_1:
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2016-09-22 09:46:50 +01:00
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case REV_FOUNDATION_FVP_v9_6:
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2014-06-26 14:27:26 +01:00
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break;
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default:
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WARN("Unrecognized Foundation FVP revision %x\n", rev);
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break;
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}
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2013-10-25 09:08:21 +01:00
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break;
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2015-03-19 19:17:53 +00:00
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case HBI_BASE_FVP:
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arm_config.flags |= ARM_CONFIG_BASE_MMAP |
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2016-02-15 11:54:14 +00:00
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ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC;
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2014-06-26 14:27:26 +01:00
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/*
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* Check for supported revisions
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* Allow future revisions to run but emit warning diagnostic
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*/
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switch (rev) {
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2015-03-19 19:17:53 +00:00
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case REV_BASE_FVP_V0:
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2014-06-26 14:27:26 +01:00
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break;
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default:
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WARN("Unrecognized Base FVP revision %x\n", rev);
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break;
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}
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2013-10-25 09:08:21 +01:00
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break;
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default:
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2014-06-26 14:27:26 +01:00
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ERROR("Unsupported board HBI number 0x%x\n", hbi);
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panic();
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2013-10-25 09:08:21 +01:00
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}
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2014-03-31 11:25:18 +01:00
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}
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2014-04-24 11:02:16 +01:00
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2015-02-26 15:25:58 +00:00
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2016-02-15 11:54:14 +00:00
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void fvp_interconnect_init(void)
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2014-04-24 11:02:16 +01:00
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{
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2016-03-24 10:12:42 +00:00
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if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) {
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#if FVP_INTERCONNECT_DRIVER == FVP_CCN
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if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
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ERROR("Unrecognized CCN variant detected. Only CCN-502"
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" is supported");
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panic();
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}
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#endif
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2016-02-15 11:54:14 +00:00
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plat_arm_interconnect_init();
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2016-03-24 10:12:42 +00:00
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}
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2014-08-04 16:11:15 +01:00
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}
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2016-02-15 11:54:14 +00:00
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void fvp_interconnect_enable(void)
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2014-08-04 16:11:15 +01:00
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{
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2016-02-15 11:54:14 +00:00
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if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
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plat_arm_interconnect_enter_coherency();
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2015-02-26 15:25:58 +00:00
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}
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2016-02-15 11:54:14 +00:00
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void fvp_interconnect_disable(void)
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2015-02-26 15:25:58 +00:00
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{
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2016-02-15 11:54:14 +00:00
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if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
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plat_arm_interconnect_exit_coherency();
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2014-04-24 11:02:16 +01:00
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}
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