2018-04-10 01:48:58 +01:00
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/*
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2017-11-21 01:14:47 +00:00
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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2018-04-10 01:48:58 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <assert.h>
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2017-06-23 09:18:58 +01:00
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#include <stdbool.h>
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#include <string.h>
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#include <arch_helpers.h>
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2018-07-06 15:33:38 +01:00
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#include <bpmp_ipc.h>
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2018-04-10 01:48:58 +01:00
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#include <common/bl_common.h>
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#include <common/debug.h>
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2017-06-23 09:18:58 +01:00
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#include <context.h>
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2018-07-06 15:33:38 +01:00
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#include <drivers/delay_timer.h>
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2018-04-10 01:48:58 +01:00
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#include <denver.h>
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2017-06-23 09:18:58 +01:00
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/psci/psci.h>
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2018-04-10 01:48:58 +01:00
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#include <mce.h>
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2017-08-10 09:01:42 +01:00
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#include <mce_private.h>
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2018-08-03 11:18:15 +01:00
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#include <memctrl_v2.h>
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2018-04-10 01:48:58 +01:00
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#include <plat/common/platform.h>
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2017-06-23 09:18:58 +01:00
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#include <se.h>
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2018-04-10 01:48:58 +01:00
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#include <smmu.h>
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2017-02-15 02:02:04 +00:00
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#include <t194_nvg.h>
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2017-11-10 21:23:34 +00:00
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#include <tegra194_private.h>
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2017-06-23 09:18:58 +01:00
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#include <tegra_platform.h>
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#include <tegra_private.h>
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2018-04-10 01:48:58 +01:00
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2017-11-10 19:04:42 +00:00
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extern uint32_t __tegra194_cpu_reset_handler_data,
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__tegra194_cpu_reset_handler_end;
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2018-04-10 01:48:58 +01:00
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/* TZDRAM offset for saving SMMU context */
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2017-11-10 19:04:42 +00:00
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#define TEGRA194_SMMU_CTX_OFFSET 16U
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2018-04-10 01:48:58 +01:00
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/* state id mask */
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2017-11-10 19:04:42 +00:00
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#define TEGRA194_STATE_ID_MASK 0xFU
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2018-04-10 01:48:58 +01:00
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/* constants to get power state's wake time */
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2017-11-10 19:04:42 +00:00
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#define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U
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#define TEGRA194_WAKE_TIME_SHIFT 4U
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2018-04-10 01:48:58 +01:00
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/* default core wake mask for CPU_SUSPEND */
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2017-09-20 10:44:43 +01:00
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#define TEGRA194_CORE_WAKE_MASK 0x180cU
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2018-04-10 01:48:58 +01:00
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2017-09-20 10:44:43 +01:00
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static struct t19x_psci_percpu_data {
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uint32_t wake_time;
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} __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT];
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2018-04-10 01:48:58 +01:00
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2017-09-20 10:44:43 +01:00
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int32_t tegra_soc_validate_power_state(uint32_t power_state,
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2018-04-10 01:48:58 +01:00
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psci_power_state_t *req_state)
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{
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2017-09-20 10:44:43 +01:00
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uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) &
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2017-11-10 19:04:42 +00:00
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TEGRA194_STATE_ID_MASK;
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2017-09-20 10:44:43 +01:00
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uint32_t cpu = plat_my_core_pos();
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int32_t ret = PSCI_E_SUCCESS;
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2018-04-10 01:48:58 +01:00
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/* save the core wake time (in TSC ticks)*/
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2017-11-10 19:04:42 +00:00
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t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK)
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<< TEGRA194_WAKE_TIME_SHIFT;
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2018-04-10 01:48:58 +01:00
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/*
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2019-12-03 16:50:57 +00:00
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* Clean t19x_percpu_data[cpu] to DRAM. This needs to be done to ensure
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* that the correct value is read in tegra_soc_pwr_domain_suspend(),
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* which is called with caches disabled. It is possible to read a stale
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* value from DRAM in that function, because the L2 cache is not flushed
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2018-04-10 01:48:58 +01:00
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* unless the cluster is entering CC6/CC7.
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*/
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2017-09-20 10:44:43 +01:00
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clean_dcache_range((uint64_t)&t19x_percpu_data[cpu],
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sizeof(t19x_percpu_data[cpu]));
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2018-04-10 01:48:58 +01:00
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/* Sanity check the requested state id */
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switch (state_id) {
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case PSTATE_ID_CORE_IDLE:
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2017-12-28 02:01:59 +00:00
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2020-05-06 06:44:20 +01:00
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if (psci_get_pstate_type(power_state) != PSTATE_TYPE_STANDBY) {
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ret = PSCI_E_INVALID_PARAMS;
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break;
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}
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2017-12-28 02:01:59 +00:00
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/* Core idle request */
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN;
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break;
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2018-04-10 01:48:58 +01:00
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default:
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ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
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2017-09-20 10:44:43 +01:00
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ret = PSCI_E_INVALID_PARAMS;
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break;
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2018-04-10 01:48:58 +01:00
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}
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2017-09-20 10:44:43 +01:00
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return ret;
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2018-04-10 01:48:58 +01:00
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}
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2017-12-28 02:01:59 +00:00
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int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
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{
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uint32_t cpu = plat_my_core_pos();
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mce_cstate_info_t cstate_info = { 0 };
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/* Program default wake mask */
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cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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/* Enter CPU idle */
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(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
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(uint64_t)TEGRA_NVG_CORE_C6,
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t19x_percpu_data[cpu].wake_time,
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0U);
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return PSCI_E_SUCCESS;
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}
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2017-09-20 10:44:43 +01:00
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int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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2018-04-10 01:48:58 +01:00
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{
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const plat_local_state_t *pwr_domain_state;
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2020-04-23 17:56:06 +01:00
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uint8_t stateid_afflvl2;
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2018-04-10 01:48:58 +01:00
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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2018-08-03 11:18:15 +01:00
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uint64_t mc_ctx_base;
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2018-04-10 01:48:58 +01:00
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uint32_t val;
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2017-05-26 00:27:42 +01:00
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mce_cstate_info_t sc7_cstate_info = {
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2017-09-20 10:44:43 +01:00
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.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6,
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2017-12-20 23:04:26 +00:00
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.ccplex = (uint32_t)TEGRA_NVG_CG_CG7,
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2017-09-20 10:44:43 +01:00
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.system = (uint32_t)TEGRA_NVG_SYSTEM_SC7,
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.system_state_force = 1U,
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.update_wake_mask = 1U,
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2017-05-26 00:27:42 +01:00
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};
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int32_t ret = 0;
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2018-04-10 01:48:58 +01:00
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/* get the state ID */
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pwr_domain_state = target_state->pwr_domain_state;
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stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
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2017-11-10 19:04:42 +00:00
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TEGRA194_STATE_ID_MASK;
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2018-04-10 01:48:58 +01:00
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2020-04-23 17:56:06 +01:00
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if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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2018-04-10 01:48:58 +01:00
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/* save 'Secure Boot' Processor Feature Config Register */
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val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
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2017-10-23 11:35:14 +01:00
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
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2018-04-10 01:48:58 +01:00
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2018-08-03 11:18:15 +01:00
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/* save MC context */
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mc_ctx_base = params_from_bl2->tzdram_base +
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tegra194_get_mc_ctx_offset();
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tegra_mc_save_context((uintptr_t)mc_ctx_base);
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2018-04-10 01:48:58 +01:00
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2017-06-23 09:18:58 +01:00
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/*
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* Suspend SE, RNG1 and PKA1 only on silcon and fpga,
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* since VDK does not support atomic se ctx save
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*/
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if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
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ret = tegra_se_suspend();
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assert(ret == 0);
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}
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2018-06-07 01:26:10 +01:00
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/* Prepare for system suspend */
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mce_update_cstate_info(&sc7_cstate_info);
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2017-04-10 23:07:39 +01:00
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2018-06-07 01:26:10 +01:00
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do {
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val = (uint32_t)mce_command_handler(
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(uint32_t)MCE_CMD_IS_SC7_ALLOWED,
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(uint32_t)TEGRA_NVG_CORE_C7,
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2017-09-20 10:44:43 +01:00
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MCE_CORE_SLEEP_TIME_INFINITE,
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0U);
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2018-06-07 01:26:10 +01:00
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} while (val == 0U);
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/* Instruct the MCE to enter system suspend state */
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ret = mce_command_handler(
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(uint64_t)MCE_CMD_ENTER_CSTATE,
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(uint64_t)TEGRA_NVG_CORE_C7,
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MCE_CORE_SLEEP_TIME_INFINITE,
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0U);
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assert(ret == 0);
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/* set system suspend state for house-keeping */
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tegra194_set_system_suspend_entry();
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2018-04-10 01:48:58 +01:00
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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2017-10-16 23:57:17 +01:00
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* Helper function to check if this is the last ON CPU in the cluster
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2018-04-10 01:48:58 +01:00
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******************************************************************************/
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2017-10-16 23:57:17 +01:00
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static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states,
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uint32_t ncpu)
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2018-04-10 01:48:58 +01:00
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{
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2017-10-16 23:57:17 +01:00
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plat_local_state_t target;
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bool last_on_cpu = true;
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2017-09-20 10:44:43 +01:00
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uint32_t num_cpus = ncpu, pos = 0;
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2018-04-10 01:48:58 +01:00
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2017-10-16 23:57:17 +01:00
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do {
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target = states[pos];
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if (target != PLAT_MAX_OFF_STATE) {
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last_on_cpu = false;
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}
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--num_cpus;
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pos++;
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} while (num_cpus != 0U);
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return last_on_cpu;
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}
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/*******************************************************************************
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* Helper function to get target power state for the cluster
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******************************************************************************/
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static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states,
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uint32_t ncpu)
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{
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uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK;
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plat_local_state_t target = states[core_pos];
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mce_cstate_info_t cstate_info = { 0 };
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2018-04-10 01:48:58 +01:00
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/* CPU off */
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2017-10-16 23:57:17 +01:00
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if (target == PLAT_MAX_OFF_STATE) {
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2018-04-10 01:48:58 +01:00
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/* Enable cluster powerdn from last CPU in the cluster */
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2017-10-16 23:57:17 +01:00
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if (tegra_last_on_cpu_in_cluster(states, ncpu)) {
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2017-07-14 21:51:44 +01:00
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2017-10-16 23:57:17 +01:00
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/* Enable CC6 state and turn off wake mask */
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cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6;
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2017-12-28 05:04:49 +00:00
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cstate_info.ccplex = (uint32_t)TEGRA_NVG_CG_CG7;
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cstate_info.system_state_force = 1;
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2017-07-14 21:51:44 +01:00
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cstate_info.update_wake_mask = 1U;
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mce_update_cstate_info(&cstate_info);
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2018-04-10 01:48:58 +01:00
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2017-07-14 21:51:44 +01:00
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} else {
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2017-10-16 23:57:17 +01:00
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2018-04-10 01:48:58 +01:00
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/* Turn off wake_mask */
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2017-07-14 21:51:44 +01:00
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cstate_info.update_wake_mask = 1U;
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mce_update_cstate_info(&cstate_info);
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2017-10-16 23:57:17 +01:00
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target = PSCI_LOCAL_STATE_RUN;
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2018-04-10 01:48:58 +01:00
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}
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}
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2017-10-16 23:57:17 +01:00
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return target;
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}
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/*******************************************************************************
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* Platform handler to calculate the proper target power level at the
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* specified affinity level
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******************************************************************************/
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plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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const plat_local_state_t *states,
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uint32_t ncpu)
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{
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plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
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uint32_t cpu = plat_my_core_pos();
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2018-04-10 01:48:58 +01:00
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/* System Suspend */
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2017-10-16 23:57:17 +01:00
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if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) {
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target = PSTATE_ID_SOC_POWERDN;
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}
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/* CPU off, CPU suspend */
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if (lvl == (uint32_t)MPIDR_AFFLVL1) {
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target = tegra_get_afflvl1_pwr_state(states, ncpu);
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2017-09-20 10:44:43 +01:00
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}
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2018-04-10 01:48:58 +01:00
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2017-10-16 23:57:17 +01:00
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/* target cluster/system state */
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return target;
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2018-04-10 01:48:58 +01:00
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}
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2017-09-20 10:44:43 +01:00
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int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
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2018-04-10 01:48:58 +01:00
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{
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const plat_local_state_t *pwr_domain_state =
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target_state->pwr_domain_state;
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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2017-09-20 10:44:43 +01:00
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uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
|
2017-11-10 19:04:42 +00:00
|
|
|
TEGRA194_STATE_ID_MASK;
|
2018-07-06 15:33:38 +01:00
|
|
|
uint64_t src_len_in_bytes = (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE;
|
2016-12-23 07:51:32 +00:00
|
|
|
uint64_t val;
|
2018-07-06 15:33:38 +01:00
|
|
|
int32_t ret = PSCI_E_SUCCESS;
|
2018-04-10 01:48:58 +01:00
|
|
|
|
|
|
|
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
|
2018-07-06 15:33:38 +01:00
|
|
|
val = params_from_bl2->tzdram_base +
|
|
|
|
tegra194_get_cpu_reset_handler_size();
|
|
|
|
|
|
|
|
/* initialise communication channel with BPMP */
|
|
|
|
ret = tegra_bpmp_ipc_init();
|
|
|
|
assert(ret == 0);
|
|
|
|
|
|
|
|
/* Enable SE clock before SE context save */
|
2018-09-13 16:47:43 +01:00
|
|
|
ret = tegra_bpmp_ipc_enable_clock(TEGRA194_CLK_SE);
|
2018-07-06 15:33:38 +01:00
|
|
|
assert(ret == 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* It is very unlikely that the BL31 image would be
|
|
|
|
* bigger than 2^32 bytes
|
|
|
|
*/
|
|
|
|
assert(src_len_in_bytes < UINT32_MAX);
|
|
|
|
|
|
|
|
if (tegra_se_calculate_save_sha256(BL31_BASE,
|
|
|
|
(uint32_t)src_len_in_bytes) != 0) {
|
|
|
|
ERROR("Hash calculation failed. Reboot\n");
|
|
|
|
(void)tegra_soc_prepare_system_reset();
|
|
|
|
}
|
|
|
|
|
2018-04-10 01:48:58 +01:00
|
|
|
/*
|
|
|
|
* The TZRAM loses power when we enter system suspend. To
|
|
|
|
* allow graceful exit from system suspend, we need to copy
|
|
|
|
* BL3-1 over to TZDRAM.
|
|
|
|
*/
|
|
|
|
val = params_from_bl2->tzdram_base +
|
2017-11-10 21:23:34 +00:00
|
|
|
tegra194_get_cpu_reset_handler_size();
|
2018-04-10 01:48:58 +01:00
|
|
|
memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
|
2018-07-06 15:33:38 +01:00
|
|
|
src_len_in_bytes);
|
|
|
|
|
|
|
|
/* Disable SE clock after SE context save */
|
2018-09-13 16:47:43 +01:00
|
|
|
ret = tegra_bpmp_ipc_disable_clock(TEGRA194_CLK_SE);
|
2018-07-06 15:33:38 +01:00
|
|
|
assert(ret == 0);
|
2018-04-10 01:48:58 +01:00
|
|
|
}
|
|
|
|
|
2018-07-06 15:33:38 +01:00
|
|
|
return ret;
|
2018-04-10 01:48:58 +01:00
|
|
|
}
|
|
|
|
|
2018-05-17 18:10:25 +01:00
|
|
|
int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
|
|
|
|
{
|
|
|
|
return PSCI_E_NOT_SUPPORTED;
|
|
|
|
}
|
|
|
|
|
2017-09-20 10:44:43 +01:00
|
|
|
int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
|
2018-04-10 01:48:58 +01:00
|
|
|
{
|
2017-09-20 10:44:43 +01:00
|
|
|
uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
|
|
|
|
uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
|
2018-04-10 01:48:58 +01:00
|
|
|
MPIDR_AFFINITY_BITS;
|
2017-09-20 10:44:43 +01:00
|
|
|
int32_t ret = 0;
|
2018-04-10 01:48:58 +01:00
|
|
|
|
2017-10-17 18:53:33 +01:00
|
|
|
if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) {
|
2018-04-10 01:48:58 +01:00
|
|
|
ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr);
|
|
|
|
return PSCI_E_NOT_PRESENT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* construct the target CPU # */
|
2017-09-20 10:44:43 +01:00
|
|
|
target_cpu += (target_cluster << 1U);
|
2018-04-10 01:48:58 +01:00
|
|
|
|
2017-09-20 10:44:43 +01:00
|
|
|
ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U);
|
|
|
|
if (ret < 0) {
|
|
|
|
return PSCI_E_DENIED;
|
|
|
|
}
|
2018-04-10 01:48:58 +01:00
|
|
|
|
|
|
|
return PSCI_E_SUCCESS;
|
|
|
|
}
|
|
|
|
|
2017-09-20 10:44:43 +01:00
|
|
|
int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
2018-04-10 01:48:58 +01:00
|
|
|
{
|
2018-09-12 22:59:08 +01:00
|
|
|
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
|
|
|
|
uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
|
2017-09-20 10:44:43 +01:00
|
|
|
uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
|
2018-09-12 22:59:08 +01:00
|
|
|
cpu_context_t *ctx = cm_get_context(NON_SECURE);
|
|
|
|
uint64_t actlr_elx;
|
2018-04-10 01:48:58 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Reset power state info for CPUs when onlining, we set
|
|
|
|
* deepest power when offlining a core but that may not be
|
|
|
|
* requested by non-secure sw which controls idle states. It
|
|
|
|
* will re-init this info from non-secure software when the
|
|
|
|
* core come online.
|
|
|
|
*/
|
2018-11-16 04:44:40 +00:00
|
|
|
actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1));
|
|
|
|
actlr_elx &= ~DENVER_CPU_PMSTATE_MASK;
|
|
|
|
actlr_elx |= DENVER_CPU_PMSTATE_C1;
|
|
|
|
write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
|
2018-04-10 01:48:58 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if we are exiting from deep sleep and restore SE
|
|
|
|
* context if we are.
|
|
|
|
*/
|
|
|
|
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
|
2017-08-10 09:01:42 +01:00
|
|
|
|
2017-12-12 22:39:15 +00:00
|
|
|
#if ENABLE_STRICT_CHECKING_MODE
|
2017-08-10 09:01:42 +01:00
|
|
|
/*
|
|
|
|
* Enable strict checking after programming the GSC for
|
|
|
|
* enabling TZSRAM and TZDRAM
|
|
|
|
*/
|
|
|
|
mce_enable_strict_checking();
|
2017-12-12 22:39:15 +00:00
|
|
|
#endif
|
2017-08-10 09:01:42 +01:00
|
|
|
|
2018-04-10 01:48:58 +01:00
|
|
|
/* Init SMMU */
|
2017-07-11 23:16:08 +01:00
|
|
|
tegra_smmu_init();
|
|
|
|
|
2017-06-23 09:18:58 +01:00
|
|
|
/* Resume SE, RNG1 and PKA1 */
|
|
|
|
tegra_se_resume();
|
|
|
|
|
2017-11-21 01:14:47 +00:00
|
|
|
/*
|
|
|
|
* Program XUSB STREAMIDs
|
|
|
|
* ======================
|
|
|
|
* T19x XUSB has support for XUSB virtualization. It will
|
|
|
|
* have one physical function (PF) and four Virtual functions
|
|
|
|
* (VF)
|
|
|
|
*
|
|
|
|
* There were below two SIDs for XUSB until T186.
|
|
|
|
* 1) #define TEGRA_SID_XUSB_HOST 0x1bU
|
|
|
|
* 2) #define TEGRA_SID_XUSB_DEV 0x1cU
|
|
|
|
*
|
|
|
|
* We have below four new SIDs added for VF(s)
|
|
|
|
* 3) #define TEGRA_SID_XUSB_VF0 0x5dU
|
|
|
|
* 4) #define TEGRA_SID_XUSB_VF1 0x5eU
|
|
|
|
* 5) #define TEGRA_SID_XUSB_VF2 0x5fU
|
|
|
|
* 6) #define TEGRA_SID_XUSB_VF3 0x60U
|
|
|
|
*
|
|
|
|
* When virtualization is enabled then we have to disable SID
|
|
|
|
* override and program above SIDs in below newly added SID
|
|
|
|
* registers in XUSB PADCTL MMIO space. These registers are
|
|
|
|
* TZ protected and so need to be done in ATF.
|
|
|
|
*
|
|
|
|
* a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
|
|
|
|
* b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
|
|
|
|
* c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
|
|
|
|
* d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
|
|
|
|
* e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
|
|
|
|
* f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
|
|
|
|
*
|
|
|
|
* This change disables SID override and programs XUSB SIDs
|
|
|
|
* in above registers to support both virtualization and
|
|
|
|
* non-virtualization platforms
|
|
|
|
*/
|
2018-03-23 17:44:40 +00:00
|
|
|
if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
|
|
|
|
|
|
|
|
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
|
2019-11-13 10:36:07 +00:00
|
|
|
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_HOST);
|
2018-03-23 17:44:40 +00:00
|
|
|
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
|
2019-11-13 10:36:07 +00:00
|
|
|
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_VF_0) == TEGRA_SID_XUSB_VF0);
|
2018-03-23 17:44:40 +00:00
|
|
|
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
|
2019-11-13 10:36:07 +00:00
|
|
|
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_VF_1) == TEGRA_SID_XUSB_VF1);
|
2018-03-23 17:44:40 +00:00
|
|
|
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
|
2019-11-13 10:36:07 +00:00
|
|
|
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_VF_2) == TEGRA_SID_XUSB_VF2);
|
2018-03-23 17:44:40 +00:00
|
|
|
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
|
2019-11-13 10:36:07 +00:00
|
|
|
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_HOST_AXI_STREAMID_VF_3) == TEGRA_SID_XUSB_VF3);
|
2018-03-23 17:44:40 +00:00
|
|
|
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
|
2019-11-13 10:36:07 +00:00
|
|
|
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
|
|
|
|
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_DEV);
|
2018-03-23 17:44:40 +00:00
|
|
|
}
|
2018-09-12 22:59:08 +01:00
|
|
|
}
|
2017-11-21 01:14:47 +00:00
|
|
|
|
2018-09-12 22:59:08 +01:00
|
|
|
/*
|
|
|
|
* Enable dual execution optimized translations for all ELx.
|
|
|
|
*/
|
|
|
|
if (enable_ccplex_lock_step != 0U) {
|
|
|
|
actlr_elx = read_actlr_el3();
|
|
|
|
actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
|
|
|
|
write_actlr_el3(actlr_elx);
|
|
|
|
|
|
|
|
actlr_elx = read_actlr_el2();
|
|
|
|
actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
|
|
|
|
write_actlr_el2(actlr_elx);
|
|
|
|
|
|
|
|
actlr_elx = read_actlr_el1();
|
|
|
|
actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
|
|
|
|
write_actlr_el1(actlr_elx);
|
2018-04-10 01:48:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return PSCI_E_SUCCESS;
|
|
|
|
}
|
|
|
|
|
2017-09-20 10:44:43 +01:00
|
|
|
int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
|
2018-04-10 01:48:58 +01:00
|
|
|
{
|
2017-09-20 10:44:43 +01:00
|
|
|
uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
|
2017-07-14 21:51:44 +01:00
|
|
|
int32_t ret = 0;
|
2018-04-10 01:48:58 +01:00
|
|
|
|
2017-09-20 10:44:43 +01:00
|
|
|
(void)target_state;
|
|
|
|
|
2018-04-10 01:48:58 +01:00
|
|
|
/* Disable Denver's DCO operations */
|
2017-09-20 10:44:43 +01:00
|
|
|
if (impl == DENVER_IMPL) {
|
2018-04-10 01:48:58 +01:00
|
|
|
denver_disable_dco();
|
2017-09-20 10:44:43 +01:00
|
|
|
}
|
2018-04-10 01:48:58 +01:00
|
|
|
|
|
|
|
/* Turn off CPU */
|
2017-09-20 10:44:43 +01:00
|
|
|
ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
|
|
|
|
(uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
|
2017-07-14 21:51:44 +01:00
|
|
|
assert(ret == 0);
|
2018-04-10 01:48:58 +01:00
|
|
|
|
|
|
|
return PSCI_E_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
__dead2 void tegra_soc_prepare_system_off(void)
|
|
|
|
{
|
|
|
|
/* System power off */
|
2017-06-14 17:59:27 +01:00
|
|
|
mce_system_shutdown();
|
2018-04-10 01:48:58 +01:00
|
|
|
|
|
|
|
wfi();
|
|
|
|
|
|
|
|
/* wait for the system to power down */
|
|
|
|
for (;;) {
|
|
|
|
;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-09-20 10:44:43 +01:00
|
|
|
int32_t tegra_soc_prepare_system_reset(void)
|
2018-04-10 01:48:58 +01:00
|
|
|
{
|
2017-06-14 17:59:27 +01:00
|
|
|
/* System reboot */
|
|
|
|
mce_system_reboot();
|
|
|
|
|
2018-04-10 01:48:58 +01:00
|
|
|
return PSCI_E_SUCCESS;
|
|
|
|
}
|