2015-03-19 18:58:55 +00:00
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/*
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2018-01-15 14:43:42 +00:00
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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2015-03-19 18:58:55 +00:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2015-03-19 18:58:55 +00:00
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*/
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2018-12-14 00:18:21 +00:00
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#include <assert.h>
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#include <platform_def.h>
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2015-03-19 18:58:55 +00:00
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#include <arch.h>
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2018-12-14 00:18:21 +00:00
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#include <bl1/bl1.h>
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#include <common/bl_common.h>
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#include <drivers/arm/sp805.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_compat.h>
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#include <plat/common/platform.h>
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2015-03-19 18:58:55 +00:00
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#include <plat_arm.h>
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2018-10-19 16:52:22 +01:00
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2015-03-19 18:58:55 +00:00
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak bl1_early_platform_setup
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#pragma weak bl1_plat_arch_setup
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#pragma weak bl1_platform_setup
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#pragma weak bl1_plat_sec_mem_layout
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2016-11-14 12:01:04 +00:00
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#pragma weak bl1_plat_prepare_exit
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2018-09-03 17:41:13 +01:00
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#pragma weak bl1_plat_get_next_image_id
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#pragma weak plat_arm_bl1_fwu_needed
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2015-03-19 18:58:55 +00:00
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2018-07-06 16:54:44 +01:00
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#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
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bl1_tzram_layout.total_base, \
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bl1_tzram_layout.total_size, \
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MT_MEMORY | MT_RW | MT_SECURE)
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2018-07-16 14:09:15 +01:00
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/*
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* If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
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* otherwise one region is defined containing both
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*/
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#if SEPARATE_CODE_AND_RODATA
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#define MAP_BL1_RO MAP_REGION_FLAT( \
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2018-07-06 16:54:44 +01:00
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BL_CODE_BASE, \
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BL1_CODE_END - BL_CODE_BASE, \
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2018-07-16 14:09:15 +01:00
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MT_CODE | MT_SECURE), \
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MAP_REGION_FLAT( \
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2018-07-06 16:54:44 +01:00
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BL1_RO_DATA_BASE, \
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BL1_RO_DATA_END \
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- BL_RO_DATA_BASE, \
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MT_RO_DATA | MT_SECURE)
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2018-07-16 14:09:15 +01:00
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#else
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#define MAP_BL1_RO MAP_REGION_FLAT( \
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BL_CODE_BASE, \
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BL1_CODE_END - BL_CODE_BASE, \
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MT_CODE | MT_SECURE)
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#endif
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2015-03-19 18:58:55 +00:00
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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static meminfo_t bl1_tzram_layout;
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2018-07-11 11:44:22 +01:00
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struct meminfo *bl1_plat_sec_mem_layout(void)
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2015-03-19 18:58:55 +00:00
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{
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return &bl1_tzram_layout;
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}
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/*******************************************************************************
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* BL1 specific platform actions shared between ARM standard platforms.
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******************************************************************************/
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void arm_bl1_early_platform_setup(void)
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{
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2015-10-06 14:01:35 +01:00
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Enable watchdog */
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sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
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#endif
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2015-03-19 18:58:55 +00:00
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/* Initialize the console to provide early debug support */
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2018-06-19 09:29:36 +01:00
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arm_console_boot_init();
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2015-03-19 18:58:55 +00:00
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
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bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
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}
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void bl1_early_platform_setup(void)
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{
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arm_bl1_early_platform_setup();
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/*
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2016-02-15 11:54:14 +00:00
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* Initialize Interconnect for this cluster during cold boot.
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2015-03-19 18:58:55 +00:00
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* No need for locks as no other CPU is active.
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*/
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2016-02-15 11:54:14 +00:00
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plat_arm_interconnect_init();
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2015-03-19 18:58:55 +00:00
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/*
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2016-02-15 11:54:14 +00:00
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* Enable Interconnect coherency for the primary CPU's cluster.
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2015-03-19 18:58:55 +00:00
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*/
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2016-02-15 11:54:14 +00:00
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plat_arm_interconnect_enter_coherency();
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2015-03-19 18:58:55 +00:00
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}
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/******************************************************************************
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* Perform the very early platform specific architecture setup shared between
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* ARM standard platforms. This only does basic initialization. Later
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* architectural setup (bl1_arch_setup()) does not do anything platform
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* specific.
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*****************************************************************************/
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void arm_bl1_plat_arch_setup(void)
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{
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2018-09-18 11:42:42 +01:00
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#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
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/*
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* Ensure ARM platforms don't use coherent memory in BL1 unless
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* cryptocell integration is enabled.
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*/
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2018-07-06 16:54:44 +01:00
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assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
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2015-03-19 18:58:55 +00:00
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#endif
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2018-07-06 16:54:44 +01:00
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const mmap_region_t bl_regions[] = {
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MAP_BL1_TOTAL,
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2018-07-16 14:09:15 +01:00
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MAP_BL1_RO,
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2018-05-23 09:27:06 +01:00
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#if USE_ROMLIB
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ARM_MAP_ROMLIB_CODE,
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ARM_MAP_ROMLIB_DATA,
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2018-09-18 11:42:42 +01:00
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#endif
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#if ARM_CRYPTOCELL_INTEG
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ARM_MAP_BL_COHERENT_RAM,
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#endif
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2018-07-06 16:54:44 +01:00
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{0}
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};
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2018-10-19 16:44:18 +01:00
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setup_page_tables(bl_regions, plat_arm_get_mmap());
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2016-07-04 11:03:49 +01:00
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#ifdef AARCH32
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2018-08-07 16:35:19 +01:00
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enable_mmu_svc_mon(0);
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2016-07-04 11:03:49 +01:00
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#else
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2016-05-18 16:11:47 +01:00
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enable_mmu_el3(0);
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2016-07-04 11:03:49 +01:00
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#endif /* AARCH32 */
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2018-05-23 09:27:06 +01:00
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arm_setup_romlib();
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2015-03-19 18:58:55 +00:00
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}
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void bl1_plat_arch_setup(void)
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{
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arm_bl1_plat_arch_setup();
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}
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/*
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* Perform the platform specific architecture setup shared between
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* ARM standard platforms.
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*/
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void arm_bl1_platform_setup(void)
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{
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/* Initialise the IO layer and register platform IO devices */
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plat_arm_io_setup();
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2018-01-15 14:43:42 +00:00
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arm_load_tb_fw_config();
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2018-07-30 13:41:52 +01:00
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#if TRUSTED_BOARD_BOOT
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/* Share the Mbed TLS heap info with other images */
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arm_bl1_set_mbedtls_heap();
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#endif /* TRUSTED_BOARD_BOOT */
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2018-09-25 11:37:23 +01:00
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2018-06-11 16:40:36 +01:00
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/*
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* Allow access to the System counter timer module and program
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* counter frequency for non secure images during FWU
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*/
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arm_configure_sys_timer();
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write_cntfrq_el0(plat_get_syscnt_freq2());
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2015-03-19 18:58:55 +00:00
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}
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void bl1_platform_setup(void)
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{
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arm_bl1_platform_setup();
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}
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2015-11-26 16:31:34 +00:00
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void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
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{
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2015-10-06 14:01:35 +01:00
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Disable watchdog before leaving BL1 */
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sp805_stop(ARM_SP805_TWDG_BASE);
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#endif
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2015-11-26 16:31:34 +00:00
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#ifdef EL3_PAYLOAD_BASE
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/*
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* Program the EL3 payload's entry point address into the CPUs mailbox
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* in order to release secondary CPUs from their holding pen and make
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* them jump there.
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*/
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2018-06-18 13:01:06 +01:00
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plat_arm_program_trusted_mailbox(ep_info->pc);
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2015-11-26 16:31:34 +00:00
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dsbsy();
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sev();
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#endif
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}
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2018-03-07 11:32:04 +00:00
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2018-09-03 17:41:13 +01:00
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/*
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* On Arm platforms, the FWU process is triggered when the FIP image has
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* been tampered with.
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*/
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int plat_arm_bl1_fwu_needed(void)
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{
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return (arm_io_is_toc_valid() != 1);
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}
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2018-03-07 11:32:04 +00:00
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/*******************************************************************************
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* The following function checks if Firmware update is needed,
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* by checking if TOC in FIP image is valid or not.
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******************************************************************************/
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unsigned int bl1_plat_get_next_image_id(void)
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{
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2018-09-03 17:41:13 +01:00
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if (plat_arm_bl1_fwu_needed() != 0)
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2018-03-07 11:32:04 +00:00
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return NS_BL1U_IMAGE_ID;
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return BL2_IMAGE_ID;
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}
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