2013-10-25 09:08:21 +01:00
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/*
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2019-02-21 16:35:07 +00:00
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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2013-10-25 09:08:21 +01:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2013-10-25 09:08:21 +01:00
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*/
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#include <arch.h>
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2014-03-18 13:46:55 +00:00
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#include <asm_macros.S>
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2014-08-14 16:19:29 +01:00
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#include <assert_macros.S>
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2018-12-14 00:18:21 +00:00
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#include <common/bl_common.h>
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#include <common/debug.h>
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2014-08-14 12:49:05 +01:00
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#include <cortex_a57.h>
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2014-08-14 11:33:56 +01:00
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#include <cpu_macros.S>
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#include <plat_macros.S>
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2013-10-25 09:08:21 +01:00
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2014-08-14 12:49:05 +01:00
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a57_disable_dcache
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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ret
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2015-03-24 14:03:57 +00:00
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endfunc cortex_a57_disable_dcache
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2014-08-14 12:49:05 +01:00
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/* ---------------------------------------------
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* Disable all types of L2 prefetches.
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* ---------------------------------------------
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*/
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func cortex_a57_disable_l2_prefetch
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2017-06-05 22:54:46 +01:00
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mrs x0, CORTEX_A57_ECTLR_EL1
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orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
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mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK
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orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK
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2014-08-14 12:49:05 +01:00
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bic x0, x0, x1
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2017-06-05 22:54:46 +01:00
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msr CORTEX_A57_ECTLR_EL1, x0
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2014-08-14 12:49:05 +01:00
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isb
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2014-09-22 12:15:26 +01:00
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dsb ish
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2014-08-14 12:49:05 +01:00
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ret
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2015-03-24 14:03:57 +00:00
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endfunc cortex_a57_disable_l2_prefetch
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2014-08-14 12:49:05 +01:00
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a57_disable_smp
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2017-06-05 22:54:46 +01:00
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mrs x0, CORTEX_A57_ECTLR_EL1
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bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT
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msr CORTEX_A57_ECTLR_EL1, x0
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2014-08-14 12:49:05 +01:00
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ret
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2015-03-24 14:03:57 +00:00
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endfunc cortex_a57_disable_smp
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2014-08-14 12:49:05 +01:00
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/* ---------------------------------------------
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* Disable debug interfaces
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* ---------------------------------------------
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*/
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func cortex_a57_disable_ext_debug
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mov x0, #1
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msr osdlr_el1, x0
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isb
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2019-02-21 16:35:49 +00:00
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#if ERRATA_A57_817169
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/*
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* Invalidate any TLB address
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*/
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mov x0, #0
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tlbi vae3, x0
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#endif
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2014-08-14 12:49:05 +01:00
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dsb sy
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ret
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2015-03-24 14:03:57 +00:00
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endfunc cortex_a57_disable_ext_debug
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2013-10-25 09:08:21 +01:00
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2014-09-22 12:11:36 +01:00
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/* --------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #806969.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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2017-01-03 11:01:51 +00:00
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* Shall clobber: x0-x17
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2014-09-22 12:11:36 +01:00
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* --------------------------------------------------
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2014-08-14 16:19:29 +01:00
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*/
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2014-09-22 12:11:36 +01:00
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func errata_a57_806969_wa
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/*
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* Compare x0 against revision r0p0
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*/
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2017-01-03 11:01:51 +00:00
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mov x17, x30
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bl check_errata_806969
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cbz x0, 1f
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2017-08-09 16:42:40 +01:00
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
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msr CORTEX_A57_CPUACTLR_EL1, x1
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2017-01-03 11:01:51 +00:00
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1:
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ret x17
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2015-03-24 14:03:57 +00:00
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endfunc errata_a57_806969_wa
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2014-09-22 12:11:36 +01:00
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2017-01-03 11:01:51 +00:00
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func check_errata_806969
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_806969
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2014-09-22 12:11:36 +01:00
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2017-02-24 11:39:22 +00:00
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #813419.
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* This applies only to revision r0p0 of Cortex A57.
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* ---------------------------------------------------
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*/
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func check_errata_813419
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/*
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* Even though this is only needed for revision r0p0, it
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* is always applied due to limitations of the current
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* errata framework.
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*/
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mov x0, #ERRATA_APPLIES
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ret
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endfunc check_errata_813419
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2014-09-22 12:11:36 +01:00
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #813420.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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2017-01-03 11:01:51 +00:00
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* Shall clobber: x0-x17
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2014-09-22 12:11:36 +01:00
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* ---------------------------------------------------
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*/
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func errata_a57_813420_wa
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/*
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* Compare x0 against revision r0p0
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*/
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2017-01-03 11:01:51 +00:00
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mov x17, x30
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bl check_errata_813420
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cbz x0, 1f
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2017-08-09 16:42:40 +01:00
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
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msr CORTEX_A57_CPUACTLR_EL1, x1
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2017-01-03 11:01:51 +00:00
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1:
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ret x17
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2015-03-24 14:03:57 +00:00
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endfunc errata_a57_813420_wa
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2014-09-22 12:11:36 +01:00
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2017-01-03 11:01:51 +00:00
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func check_errata_813420
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_813420
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2019-02-21 16:35:07 +00:00
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #814670.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------
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*/
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func errata_a57_814670_wa
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/*
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* Compare x0 against revision r0p0
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*/
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mov x17, x30
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bl check_errata_814670
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cbz x0, 1f
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION
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msr CORTEX_A57_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a57_814670_wa
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func check_errata_814670
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_814670
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2019-02-21 16:35:49 +00:00
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/* ----------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #817169.
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* This applies only to revision <= r0p1 of Cortex A57.
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* ----------------------------------------------------
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*/
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func check_errata_817169
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/*
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* Even though this is only needed for revision <= r0p1, it
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* is always applied because of the low cost of the workaround.
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*/
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mov x0, #ERRATA_APPLIES
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ret
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endfunc check_errata_817169
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2016-01-13 14:57:38 +00:00
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/* --------------------------------------------------------------------
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* Disable the over-read from the LDNP instruction.
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*
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* This applies to all revisions <= r1p2. The performance degradation
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* observed with LDNP/STNP has been fixed on r1p3 and onwards.
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*
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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2017-01-03 11:01:51 +00:00
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* Shall clobber: x0-x17
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2016-01-13 14:57:38 +00:00
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* ---------------------------------------------------------------------
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*/
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func a57_disable_ldnp_overread
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/*
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* Compare x0 against revision r1p2
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*/
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2017-01-03 11:01:51 +00:00
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mov x17, x30
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bl check_errata_disable_ldnp_overread
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cbz x0, 1f
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2017-08-09 16:42:40 +01:00
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
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msr CORTEX_A57_CPUACTLR_EL1, x1
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2017-01-03 11:01:51 +00:00
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1:
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ret x17
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2016-01-13 14:57:38 +00:00
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endfunc a57_disable_ldnp_overread
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2017-01-03 11:01:51 +00:00
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func check_errata_disable_ldnp_overread
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mov x1, #0x12
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b cpu_rev_var_ls
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endfunc check_errata_disable_ldnp_overread
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2016-04-14 13:32:31 +01:00
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #826974.
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* This applies only to revision <= r1p1 of Cortex A57.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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2017-01-03 11:01:51 +00:00
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* Shall clobber: x0-x17
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2016-04-14 13:32:31 +01:00
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* ---------------------------------------------------
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*/
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func errata_a57_826974_wa
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/*
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* Compare x0 against revision r1p1
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*/
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2017-01-03 11:01:51 +00:00
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mov x17, x30
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bl check_errata_826974
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cbz x0, 1f
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2017-08-09 16:42:40 +01:00
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
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msr CORTEX_A57_CPUACTLR_EL1, x1
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2017-01-03 11:01:51 +00:00
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1:
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ret x17
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2016-04-14 13:32:31 +01:00
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endfunc errata_a57_826974_wa
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2017-01-03 11:01:51 +00:00
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func check_errata_826974
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_826974
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2016-04-14 14:24:13 +01:00
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #826977.
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* This applies only to revision <= r1p1 of Cortex A57.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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2017-01-03 11:01:51 +00:00
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* Shall clobber: x0-x17
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2016-04-14 14:24:13 +01:00
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* ---------------------------------------------------
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*/
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func errata_a57_826977_wa
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/*
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* Compare x0 against revision r1p1
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*/
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2017-01-03 11:01:51 +00:00
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mov x17, x30
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bl check_errata_826977
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cbz x0, 1f
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2017-08-09 16:42:40 +01:00
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
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msr CORTEX_A57_CPUACTLR_EL1, x1
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2017-01-03 11:01:51 +00:00
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1:
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ret x17
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2016-04-14 14:24:13 +01:00
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endfunc errata_a57_826977_wa
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2017-01-03 11:01:51 +00:00
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func check_errata_826977
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_826977
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2016-04-14 14:04:48 +01:00
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #828024.
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* This applies only to revision <= r1p1 of Cortex A57.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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2017-01-03 11:01:51 +00:00
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* Shall clobber: x0-x17
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2016-04-14 14:04:48 +01:00
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* ---------------------------------------------------
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*/
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func errata_a57_828024_wa
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/*
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* Compare x0 against revision r1p1
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*/
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2017-01-03 11:01:51 +00:00
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mov x17, x30
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bl check_errata_828024
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cbz x0, 1f
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2017-08-09 16:42:40 +01:00
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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2016-04-14 14:04:48 +01:00
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/*
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* Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
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* instructions here because the resulting bitmask doesn't fit in a
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* 16-bit value so it cannot be encoded in a single instruction.
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*/
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2017-08-09 16:42:40 +01:00
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
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orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \
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CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING)
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msr CORTEX_A57_CPUACTLR_EL1, x1
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2017-01-03 11:01:51 +00:00
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1:
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ret x17
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2016-04-14 14:04:48 +01:00
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endfunc errata_a57_828024_wa
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2016-04-14 13:32:31 +01:00
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2017-01-03 11:01:51 +00:00
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func check_errata_828024
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_828024
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2016-04-14 14:18:07 +01:00
|
|
|
/* ---------------------------------------------------
|
|
|
|
* Errata Workaround for Cortex A57 Errata #829520.
|
|
|
|
* This applies only to revision <= r1p2 of Cortex A57.
|
|
|
|
* Inputs:
|
|
|
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
2017-01-03 11:01:51 +00:00
|
|
|
* Shall clobber: x0-x17
|
2016-04-14 14:18:07 +01:00
|
|
|
* ---------------------------------------------------
|
|
|
|
*/
|
|
|
|
func errata_a57_829520_wa
|
|
|
|
/*
|
|
|
|
* Compare x0 against revision r1p2
|
|
|
|
*/
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x17, x30
|
|
|
|
bl check_errata_829520
|
|
|
|
cbz x0, 1f
|
2017-08-09 16:42:40 +01:00
|
|
|
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
|
|
|
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
|
|
|
|
msr CORTEX_A57_CPUACTLR_EL1, x1
|
2017-01-03 11:01:51 +00:00
|
|
|
1:
|
|
|
|
ret x17
|
2016-04-14 14:18:07 +01:00
|
|
|
endfunc errata_a57_829520_wa
|
|
|
|
|
2017-01-03 11:01:51 +00:00
|
|
|
func check_errata_829520
|
|
|
|
mov x1, #0x12
|
|
|
|
b cpu_rev_var_ls
|
|
|
|
endfunc check_errata_829520
|
|
|
|
|
2016-04-21 11:10:52 +01:00
|
|
|
/* ---------------------------------------------------
|
|
|
|
* Errata Workaround for Cortex A57 Errata #833471.
|
|
|
|
* This applies only to revision <= r1p2 of Cortex A57.
|
|
|
|
* Inputs:
|
|
|
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
2017-01-03 11:01:51 +00:00
|
|
|
* Shall clobber: x0-x17
|
2016-04-21 11:10:52 +01:00
|
|
|
* ---------------------------------------------------
|
|
|
|
*/
|
|
|
|
func errata_a57_833471_wa
|
|
|
|
/*
|
|
|
|
* Compare x0 against revision r1p2
|
|
|
|
*/
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x17, x30
|
|
|
|
bl check_errata_833471
|
|
|
|
cbz x0, 1f
|
2017-08-09 16:42:40 +01:00
|
|
|
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
|
|
|
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
|
|
|
|
msr CORTEX_A57_CPUACTLR_EL1, x1
|
2017-01-03 11:01:51 +00:00
|
|
|
1:
|
|
|
|
ret x17
|
2016-04-21 11:10:52 +01:00
|
|
|
endfunc errata_a57_833471_wa
|
|
|
|
|
2017-01-03 11:01:51 +00:00
|
|
|
func check_errata_833471
|
|
|
|
mov x1, #0x12
|
|
|
|
b cpu_rev_var_ls
|
|
|
|
endfunc check_errata_833471
|
|
|
|
|
2017-08-02 16:35:04 +01:00
|
|
|
/* --------------------------------------------------
|
|
|
|
* Errata Workaround for Cortex A57 Errata #859972.
|
|
|
|
* This applies only to revision <= r1p3 of Cortex A57.
|
|
|
|
* Inputs:
|
|
|
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
|
|
|
* Shall clobber:
|
|
|
|
* --------------------------------------------------
|
|
|
|
*/
|
|
|
|
func errata_a57_859972_wa
|
|
|
|
mov x17, x30
|
|
|
|
bl check_errata_859972
|
|
|
|
cbz x0, 1f
|
|
|
|
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
|
|
|
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH
|
|
|
|
msr CORTEX_A57_CPUACTLR_EL1, x1
|
|
|
|
1:
|
|
|
|
ret x17
|
|
|
|
endfunc errata_a57_859972_wa
|
|
|
|
|
|
|
|
func check_errata_859972
|
|
|
|
mov x1, #0x13
|
|
|
|
b cpu_rev_var_ls
|
|
|
|
endfunc check_errata_859972
|
|
|
|
|
2018-01-16 10:32:47 +00:00
|
|
|
func check_errata_cve_2017_5715
|
|
|
|
#if WORKAROUND_CVE_2017_5715
|
|
|
|
mov x0, #ERRATA_APPLIES
|
|
|
|
#else
|
|
|
|
mov x0, #ERRATA_MISSING
|
|
|
|
#endif
|
|
|
|
ret
|
|
|
|
endfunc check_errata_cve_2017_5715
|
|
|
|
|
2018-04-05 14:38:26 +01:00
|
|
|
func check_errata_cve_2018_3639
|
|
|
|
#if WORKAROUND_CVE_2018_3639
|
|
|
|
mov x0, #ERRATA_APPLIES
|
|
|
|
#else
|
|
|
|
mov x0, #ERRATA_MISSING
|
|
|
|
#endif
|
|
|
|
ret
|
|
|
|
endfunc check_errata_cve_2018_3639
|
|
|
|
|
2014-09-22 12:11:36 +01:00
|
|
|
/* -------------------------------------------------
|
|
|
|
* The CPU Ops reset function for Cortex-A57.
|
2017-01-03 11:01:51 +00:00
|
|
|
* Shall clobber: x0-x19
|
2014-09-22 12:11:36 +01:00
|
|
|
* -------------------------------------------------
|
|
|
|
*/
|
|
|
|
func cortex_a57_reset_func
|
|
|
|
mov x19, x30
|
2017-01-03 11:01:51 +00:00
|
|
|
bl cpu_get_rev_var
|
|
|
|
mov x18, x0
|
2014-09-22 12:11:36 +01:00
|
|
|
|
|
|
|
#if ERRATA_A57_806969
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x0, x18
|
2014-09-22 12:11:36 +01:00
|
|
|
bl errata_a57_806969_wa
|
2014-08-14 16:19:29 +01:00
|
|
|
#endif
|
|
|
|
|
2014-09-22 12:11:36 +01:00
|
|
|
#if ERRATA_A57_813420
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x0, x18
|
2014-09-22 12:11:36 +01:00
|
|
|
bl errata_a57_813420_wa
|
|
|
|
#endif
|
2014-11-20 18:09:41 +00:00
|
|
|
|
2019-02-21 16:35:07 +00:00
|
|
|
#if ERRATA_A57_814670
|
|
|
|
mov x0, x18
|
|
|
|
bl errata_a57_814670_wa
|
|
|
|
#endif
|
|
|
|
|
2016-01-13 14:57:38 +00:00
|
|
|
#if A57_DISABLE_NON_TEMPORAL_HINT
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x0, x18
|
2016-01-13 14:57:38 +00:00
|
|
|
bl a57_disable_ldnp_overread
|
|
|
|
#endif
|
|
|
|
|
2016-04-14 13:32:31 +01:00
|
|
|
#if ERRATA_A57_826974
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x0, x18
|
2016-04-14 13:32:31 +01:00
|
|
|
bl errata_a57_826974_wa
|
|
|
|
#endif
|
|
|
|
|
2016-04-14 14:24:13 +01:00
|
|
|
#if ERRATA_A57_826977
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x0, x18
|
2016-04-14 14:24:13 +01:00
|
|
|
bl errata_a57_826977_wa
|
|
|
|
#endif
|
|
|
|
|
2016-04-14 14:04:48 +01:00
|
|
|
#if ERRATA_A57_828024
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x0, x18
|
2016-04-14 14:04:48 +01:00
|
|
|
bl errata_a57_828024_wa
|
|
|
|
#endif
|
2016-04-14 14:18:07 +01:00
|
|
|
|
|
|
|
#if ERRATA_A57_829520
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x0, x18
|
2016-04-14 14:18:07 +01:00
|
|
|
bl errata_a57_829520_wa
|
|
|
|
#endif
|
|
|
|
|
2016-04-21 11:10:52 +01:00
|
|
|
#if ERRATA_A57_833471
|
2017-01-03 11:01:51 +00:00
|
|
|
mov x0, x18
|
2016-04-21 11:10:52 +01:00
|
|
|
bl errata_a57_833471_wa
|
|
|
|
#endif
|
|
|
|
|
2017-08-02 16:35:04 +01:00
|
|
|
#if ERRATA_A57_859972
|
|
|
|
mov x0, x18
|
|
|
|
bl errata_a57_859972_wa
|
|
|
|
#endif
|
|
|
|
|
2017-11-30 14:53:53 +00:00
|
|
|
#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
|
2018-04-06 15:29:34 +01:00
|
|
|
adr x0, wa_cve_2017_5715_mmu_vbar
|
2017-11-30 14:53:53 +00:00
|
|
|
msr vbar_el3, x0
|
2018-06-07 13:20:19 +01:00
|
|
|
/* isb will be performed before returning from this function */
|
2017-11-30 14:53:53 +00:00
|
|
|
#endif
|
|
|
|
|
2018-04-05 14:38:26 +01:00
|
|
|
#if WORKAROUND_CVE_2018_3639
|
|
|
|
mrs x0, CORTEX_A57_CPUACTLR_EL1
|
|
|
|
orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
|
|
|
|
msr CORTEX_A57_CPUACTLR_EL1, x0
|
|
|
|
isb
|
|
|
|
dsb sy
|
|
|
|
#endif
|
|
|
|
|
2013-10-25 09:08:21 +01:00
|
|
|
/* ---------------------------------------------
|
2016-01-29 14:37:58 +00:00
|
|
|
* Enable the SMP bit.
|
2013-10-25 09:08:21 +01:00
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
2017-06-05 22:54:46 +01:00
|
|
|
mrs x0, CORTEX_A57_ECTLR_EL1
|
|
|
|
orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT
|
|
|
|
msr CORTEX_A57_ECTLR_EL1, x0
|
2014-04-28 12:28:39 +01:00
|
|
|
isb
|
2014-09-22 12:11:36 +01:00
|
|
|
ret x19
|
2015-03-24 14:03:57 +00:00
|
|
|
endfunc cortex_a57_reset_func
|
2014-08-14 11:33:56 +01:00
|
|
|
|
2014-09-22 12:11:36 +01:00
|
|
|
/* ----------------------------------------------------
|
|
|
|
* The CPU Ops core power down function for Cortex-A57.
|
|
|
|
* ----------------------------------------------------
|
|
|
|
*/
|
2014-08-14 12:49:05 +01:00
|
|
|
func cortex_a57_core_pwr_dwn
|
|
|
|
mov x18, x30
|
|
|
|
|
|
|
|
/* ---------------------------------------------
|
|
|
|
* Turn off caches.
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
bl cortex_a57_disable_dcache
|
|
|
|
|
|
|
|
/* ---------------------------------------------
|
|
|
|
* Disable the L2 prefetches.
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
bl cortex_a57_disable_l2_prefetch
|
|
|
|
|
|
|
|
/* ---------------------------------------------
|
2014-09-02 10:47:33 +01:00
|
|
|
* Flush L1 caches.
|
2014-08-14 12:49:05 +01:00
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
mov x0, #DCCISW
|
2014-09-02 10:47:33 +01:00
|
|
|
bl dcsw_op_level1
|
2014-08-14 12:49:05 +01:00
|
|
|
|
|
|
|
/* ---------------------------------------------
|
|
|
|
* Come out of intra cluster coherency
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
bl cortex_a57_disable_smp
|
|
|
|
|
|
|
|
/* ---------------------------------------------
|
|
|
|
* Force the debug interfaces to be quiescent
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
mov x30, x18
|
|
|
|
b cortex_a57_disable_ext_debug
|
2015-03-24 14:03:57 +00:00
|
|
|
endfunc cortex_a57_core_pwr_dwn
|
2014-08-14 12:49:05 +01:00
|
|
|
|
2014-09-22 12:11:36 +01:00
|
|
|
/* -------------------------------------------------------
|
|
|
|
* The CPU Ops cluster power down function for Cortex-A57.
|
|
|
|
* -------------------------------------------------------
|
|
|
|
*/
|
2014-08-14 12:49:05 +01:00
|
|
|
func cortex_a57_cluster_pwr_dwn
|
|
|
|
mov x18, x30
|
|
|
|
|
|
|
|
/* ---------------------------------------------
|
|
|
|
* Turn off caches.
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
bl cortex_a57_disable_dcache
|
|
|
|
|
|
|
|
/* ---------------------------------------------
|
|
|
|
* Disable the L2 prefetches.
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
bl cortex_a57_disable_l2_prefetch
|
|
|
|
|
2014-09-22 14:13:34 +01:00
|
|
|
#if !SKIP_A57_L1_FLUSH_PWR_DWN
|
2014-09-02 10:47:33 +01:00
|
|
|
/* -------------------------------------------------
|
|
|
|
* Flush the L1 caches.
|
|
|
|
* -------------------------------------------------
|
|
|
|
*/
|
|
|
|
mov x0, #DCCISW
|
|
|
|
bl dcsw_op_level1
|
2014-09-22 14:13:34 +01:00
|
|
|
#endif
|
2014-08-14 12:49:05 +01:00
|
|
|
/* ---------------------------------------------
|
|
|
|
* Disable the optional ACP.
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
bl plat_disable_acp
|
|
|
|
|
2014-09-02 10:47:33 +01:00
|
|
|
/* -------------------------------------------------
|
|
|
|
* Flush the L2 caches.
|
|
|
|
* -------------------------------------------------
|
2014-08-14 12:49:05 +01:00
|
|
|
*/
|
|
|
|
mov x0, #DCCISW
|
2014-09-02 10:47:33 +01:00
|
|
|
bl dcsw_op_level2
|
2014-08-14 12:49:05 +01:00
|
|
|
|
|
|
|
/* ---------------------------------------------
|
|
|
|
* Come out of intra cluster coherency
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
bl cortex_a57_disable_smp
|
|
|
|
|
|
|
|
/* ---------------------------------------------
|
|
|
|
* Force the debug interfaces to be quiescent
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
|
|
|
mov x30, x18
|
|
|
|
b cortex_a57_disable_ext_debug
|
2015-03-24 14:03:57 +00:00
|
|
|
endfunc cortex_a57_cluster_pwr_dwn
|
2014-08-14 12:49:05 +01:00
|
|
|
|
2017-01-03 11:01:51 +00:00
|
|
|
#if REPORT_ERRATA
|
|
|
|
/*
|
|
|
|
* Errata printing function for Cortex A57. Must follow AAPCS.
|
|
|
|
*/
|
|
|
|
func cortex_a57_errata_report
|
|
|
|
stp x8, x30, [sp, #-16]!
|
|
|
|
|
|
|
|
bl cpu_get_rev_var
|
|
|
|
mov x8, x0
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Report all errata. The revision-variant information is passed to
|
|
|
|
* checking functions of each errata.
|
|
|
|
*/
|
|
|
|
report_errata ERRATA_A57_806969, cortex_a57, 806969
|
2017-02-24 11:39:22 +00:00
|
|
|
report_errata ERRATA_A57_813419, cortex_a57, 813419
|
2017-01-03 11:01:51 +00:00
|
|
|
report_errata ERRATA_A57_813420, cortex_a57, 813420
|
2019-02-21 16:35:07 +00:00
|
|
|
report_errata ERRATA_A57_814670, cortex_a57, 814670
|
2019-02-21 16:35:49 +00:00
|
|
|
report_errata ERRATA_A57_817169, cortex_a57, 817169
|
2017-01-03 11:01:51 +00:00
|
|
|
report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
|
|
|
|
disable_ldnp_overread
|
|
|
|
report_errata ERRATA_A57_826974, cortex_a57, 826974
|
|
|
|
report_errata ERRATA_A57_826977, cortex_a57, 826977
|
|
|
|
report_errata ERRATA_A57_828024, cortex_a57, 828024
|
|
|
|
report_errata ERRATA_A57_829520, cortex_a57, 829520
|
|
|
|
report_errata ERRATA_A57_833471, cortex_a57, 833471
|
2017-08-02 16:35:04 +01:00
|
|
|
report_errata ERRATA_A57_859972, cortex_a57, 859972
|
2018-01-16 10:32:47 +00:00
|
|
|
report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715
|
2018-04-05 14:38:26 +01:00
|
|
|
report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639
|
2017-01-03 11:01:51 +00:00
|
|
|
|
|
|
|
ldp x8, x30, [sp], #16
|
|
|
|
ret
|
|
|
|
endfunc cortex_a57_errata_report
|
|
|
|
#endif
|
|
|
|
|
2014-08-14 13:36:41 +01:00
|
|
|
/* ---------------------------------------------
|
|
|
|
* This function provides cortex_a57 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a57_regs, "aS"
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cortex_a57_regs: /* The ascii list of register names to be reported */
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2016-07-01 08:22:41 +01:00
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.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
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2014-08-14 13:36:41 +01:00
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func cortex_a57_cpu_reg_dump
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adr x6, cortex_a57_regs
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2017-06-05 22:54:46 +01:00
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mrs x8, CORTEX_A57_ECTLR_EL1
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mrs x9, CORTEX_A57_MERRSR_EL1
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mrs x10, CORTEX_A57_L2MERRSR_EL1
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2014-08-14 13:36:41 +01:00
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ret
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2015-03-24 14:03:57 +00:00
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endfunc cortex_a57_cpu_reg_dump
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2014-08-14 13:36:41 +01:00
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2018-05-16 11:36:14 +01:00
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declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \
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2016-11-18 12:58:28 +00:00
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cortex_a57_reset_func, \
|
2018-03-12 14:47:09 +00:00
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check_errata_cve_2017_5715, \
|
2018-05-16 11:36:14 +01:00
|
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CPU_NO_EXTRA2_FUNC, \
|
2016-11-18 12:58:28 +00:00
|
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cortex_a57_core_pwr_dwn, \
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cortex_a57_cluster_pwr_dwn
|