These files are needed during boot, but they were missing
for semihosting.
With this patch, the list of files is complete enough to
boot on ATF platform via semihosting.
Change-Id: I2f0ca25983a6e18096f040780776f19f8040ea79
Signed-off-by: stsp@users.sourceforge.net
The rpi4 has a single nonstandard ECAM. It is broken
into two pieces, the root port registers, and a window
to a single device's config space which can be moved
between devices. Now that we have widened the page
tables/MMIO window, we can create a read/write acces
functions that are called by the SMCCC/PCI API.
As an example platform, the rpi4 single device ECAM
region quirk is pretty straightforward. The assumption
here is that a lower level (uefi) has configured and
initialized the PCI root to match the values we are
using here.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: Ie1ffa8fe9aa1d3c62e6aa84746a949c1009162e0
Now that we have adjusted the address map, added the
SMC conduit code, and the RPi4 PCI callbacks, lets
add the flags to enable everything in the build.
By default this service is disabled because the
expectation is that its only useful in a UEFI+ACPI
environment.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: I2a3cac6d63ba8119d3b711db121185816b89f8a2
* changes:
refactor(plat/allwinner): clean up platform definitions
refactor(plat/allwinner): do not map BL32 DRAM at EL3
refactor(plat/allwinner): map SRAM as device memory by default
refactor(plat/allwinner): rename static mmap region constant
feat(bl_common): import BL_NOBITS_{BASE,END} when defined
Recent changes to enable SVE for the secure world have disabled AMU
extension by default in the reset value of CPTR_EL3 register. So the
platform has to enable this extension explicitly.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I7d930d96ec22d7c3db961411370564bece0ce272
Group the SCP base/size definitions in a more logical location.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id43f9b468d7d855a2413173d674a5ee666527808
BL31 does not appear to ever access the DRAM allocated to BL32,
so there is no need to map it at EL3.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie8727b793e53ea14517894942266f6da0333eb74
The SRAM on Allwinner platforms is shared between BL31 and coprocessor
firmware. Previously, SRAM was mapped as normal memory by default.
This scheme requires carveouts and cache maintenance code for proper
synchronization with the coprocessor.
A better scheme is to only map pages owned by BL31 as normal memory,
and leave everything else as device memory. This removes the need for
cache maintenance, and it makes the mapping for BL31 RW data explicit
instead of magic.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348
This constant specifically refers to the number of static mmap regions.
Rename it to make that clear.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I475c037777ce2a10db2631ec0e7446bb73590a36
At this stage of development Non Volatile counters are not implemented
in the Diphda platform.
This commit disables their use during the Trusted Board Boot by
overriding the NV counters get/set functions.
Change-Id: I8dcbebe0281cc4d0837c283ff637e20b850988ef
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.
Diphda uses a FIP image located in the flash. The FIP contains the
following components:
- BL2
- BL31
- BL32
- BL32 SPMC manifest
- BL33
- The TBB certificates
The board boot relies on CoT (chain of trust). The trusted-firmware-a
BL2 is extracted from the FIP and verified by the Secure Enclave
processor. BL2 verification relies on the signature area at the
beginning of the BL2 image. This area is needed by the SecureEnclave
bootloader.
Then, the application processor is released from reset and starts by
executing BL2.
BL2 performs the actions described in the trusted-firmware-a TBB design
document.
Signed-off-by: Rui Miguel Silva <rui.silva@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d
* changes:
refactor(plat/arm): use mmio* functions to read/write NVFLAGS registers
refactor(plat/arm): mark the flash region as read-only
refactor(plat/arm): update NV flags on image load/authentication failure
* changes:
fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive
refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables
refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB
refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable
fix(plat/marvell/a3k): Fix check for external dependences
fix(plat/marvell/a8k): Add missing build dependency for BLE target
fix(plat/marvell/a8k): Correctly set include directories for individual targets
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
There is a error setting for SPM, so we need to fix this issue.
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a831fe48fd5bc3da9904db14c8a57
This change adds 208 bytes to PMUSRAM, pushing the end of text from
0xff3b0de0 to 0xff3b0eb0, which is still shy of the maximum
0xff3b1000.
Further, this skips enabling the watchdog when it's not being used
elsewhere, as you can't turn the watchdog off.
Change-Id: I2e6fa3c7e01f2be6b32ce04ce479edf64e278554
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
For UART secure boot it is required also TIMN image, so pack it into
uart-images.tgz.bin archive which is created by mrvl_uart target.
$(TIMN_IMAGE) and $(TIM_IMAGE) variables are used only for UART images
so their content needs to be initialized from $(TIMN_UART_CFG) and
$(TIM_UART_CFG) config files. And not from $(TIMN_CFG) and $(TIM_CFG) as
it is now because they are not generated during mrvl_uart target. Fix it
to allow building mrvl_uart target before mrvl_flash target.
To match usage of these variables, rename them to $(TIMN_UART_IMAGE) and
$(TIM_UART_IMAGE).
To not complicate rule for building uart-images.tgz.bin archive, set
list of image files into a new $(UART_IMAGES) variable.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I83b980abb4047a3afb3ce3026842e1d873c490bf
For TIM config file use TIM name instead of DOIMAGE and use underscores
to make variable names more readable.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1282ce11f1431c15458a143ae7bfcee85eed2432
Armada 3700 uses external TBB tool for creating images and does not use
internal TF-A doimage tool from tools/marvell/doimage/
Therefore set correct name of variable.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I38a94dca78d483de4c79da597c032e1e5d06d92d
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Extranet anymore. Public version on github repository contains all
patches and is working fine, so for public TF-A builds use only public
external dependencies from git.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
BLE source files depend on external Marvell mv-ddr-marvell tree
(specified in $(MV_DDR_PATH) variable) and its header files. Add
dependency on $(MV_DDR_LIB) target which checks that variable
$(MV_DDR_PATH) is correctly set and ensures that make completes
compilation of mv-ddr-marvell tree.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I73968b24c45d9af1e3500b8db7a24bb4eb2bfa47
Do not set all include directories, including those for external targets
in one PLAT_INCLUDES variable.
Instead split them into variables:
* $(PLAT_INCLUDES) for all TF-A BL images
* BLE target specific $(PLAT_INCLUDES) only for Marvell BLE image
* $(MV_DDR_INCLUDES) for targets in external Marvell mv-ddr-marvell tree
Include directory $(CURDIR)/drivers/marvell is required by TF-A BL
images, so move it from ble.mk to a8k_common.mk.
Include directory $(MV_DDR_PATH) is needed only by Marvell BLE image, so
move it into BLE target specific $(PLAT_INCLUDES) variable.
And remaining include directories specified in ble.mk are needed only
for building external dependences from Marvell mv-ddr tree, so move them
into $(MV_DDR_INCLUDES) variable and correctly use it in $(MV_DDR_LIB)
target.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I331f7de675dca2bc70733d56b768f00d56ae4a67
Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded at some
specific location and require user to specify correct path to mv_ddr
source code via MV_DDR_PATH build option.
TF-A code for Armada 37x0 platform also depends on mv_ddr source code
and already requires passing correct MV_DDR_PATH build option.
So for A8K implement same checks for validity of MV_DDR_PATH option as
are already used by TF-A code for Armada 37x0 platform.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are not reading
status from IPI payload data. Use sync method which
reads actual return status from IPI payload.
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I6f568b85d0da639c264f507122e3015807d8423d
All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are not reading
status from IPI payload data. Use sync method which
reads actual return status from IPI payload.
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I78f9c061a80cee6d524ade4ef124ca88ce1848cf
Used mmio* functions to read/write NVFLAGS registers to avoid
possibile reordering of instructions by compiler.
Change-Id: Iae50ac30e5413259cf8554f0fff47512ad83b0fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
In the FVP platform, BL1 uses flash only for read purpose
hence marked this flash region as read-only.
Change-Id: I3b57130fd4f3b4df522ac075f66e9799f237ebb7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Erasing the FIP TOC header present in a flash is replaced by updating NV
flags with an error code on image load/authentication failure.
BL1 component uses these NV flags to detect whether a firmware update is
needed or not.
These NV flags get cleared once the firmware update gets completed.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6232a0db07c89b2373b7b9d28acd37df6203d914
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.
Change-Id: I3237199bc217bd3682f51d31284db5fd0324b396
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
In the qemu memory map 1GB and up is RAM. Change the
size of NS DRAM to 3GB to support VM's with more
memory requirements.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Change-Id: If15cf3b9d3e2e7876c40ce888f22e887893fe696
* changes:
feat(plat/mediatek/mt8195): add SPM suspend driver
feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
feat(plat/mediatek/mt8195): add support for PTP3
fix(plat/mediatek/mt8195): extend MMU region size
Support DRAM/MAINPLL/26M off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Ib8502f9b0b4e47aa405e5449f0b6d483bd3f5d77