Commit Graph

1310 Commits

Author SHA1 Message Date
Manish Pandey 24ce8d134a Merge "fix(nxp-drivers): ddr: corrects mapping of HNFs nodes" into integration 2022-01-27 23:05:51 +01:00
Lionel Debieve 591d80c8b1 refactor(st-clock): update STGEN management
Rework STGEN config function, and move it to stm32mp_clkfunc.c file.

Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-27 18:06:36 +01:00
Yann Gautier 7418cf3979 feat(st-clock): assign clocks to the correct BL
Some clocks are only required in BL2, like boot devices clocks:
FMC, QSPI.
Some clocks are only used in BL32: Timers, devices that need special
care for independent reset.

Change-Id: Id4ba99afeea5095f419a86f7dc6423192c628d82
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-27 18:06:36 +01:00
Yann Gautier 3d69149a7e feat(st-clock): do not refcount on non-secure clocks in bl32
This change removes reference counting support in clock gating
implementation for clocks that rely on non-secure only RCC resources.
As RCC registers are accessed straight by non-secure world for these
clocks, secure world cannot safely store the clock state and even
disabling such clock from secure world can jeopardize the non-secure
world clock management framework and drivers.

As a consequence, for such clocks, stm32_clock_enable() forces the clock
ON without any increment of a refcount and stm32_clock_disable() does
not disable the clock.

Change-Id: I0cc159b36a25dbc8676f05edf2668ae63c640537
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2022-01-27 18:06:36 +01:00
Yann Gautier aaa09b713c feat(st-clock): define secure and non-secure gate clocks
Array stm32mp1_clk_gate[] defines the clock resources. This change
add a secure attribute to the clock: secure upon RCC[TZEN] (SEC),
secure upon RCC[TZEN] and RCC[MCKPROT] (MKP) or always accessible
from non-secure (N_S).

At init, lookup clock tree to check if any of the secure clocks
is derived from PLL3 in which case PLL3 shall be secure.

Note that this change does not grow byte size of stm32mp1_clk_gate[].

Change-Id: I933d8a30007f3c72f755aa1ef6d7e6bcfabbfa9e
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-27 18:06:36 +01:00
Yann Gautier 2444d2314c refactor(st-clock): use refcnt instead of secure status
Rework the internal functions __stm32mp1_clk_enable/disable to check for
reference count instead of secure status for a clock.
Some functions now unused can be removed.

Change-Id: Ie4359110d7144229f85c961dcd5a019222c3fd25
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-27 18:06:07 +01:00
Sughosh Ganu 40b085bddf feat(fwu): simplify the assert to check for fwu init
Simplify the assert to check if the FWU subsystem has been initialised
in the fwu_is_trial_run_state function.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I428668470ebd4b67e68777a62d5732cb96841ab9
2022-01-27 18:09:02 +05:30
Sughosh Ganu 9adce87efc feat(fwu): add a function to pass metadata structure to platforms
Add a helper function to pass the metadata structure to the
platforms. Platforms can then read the metadata structure and pass the
boot index value, i.e. the bank(partition) from which the firmware
images were booted, to the Update Agent.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I571179b9baa0fbc4d0f08d7a6e3b50c0c7165c5c
2022-01-27 18:09:02 +05:30
Sughosh Ganu 3cb1065581 feat(partition): add a function to identify a partition by GUID
With the GPT partition scheme, a partition can be identified using
it's UniquePartitionGUID, instead of it's name. Add a function to
identify the partition based on this GUID value. This functionality is
useful in identification of a partition whose UniquePartitionGUID
value is known.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I543f794e1f7773f969968a6bce85ecca6f6a1659
2022-01-27 18:09:02 +05:30
Sughosh Ganu 7585ec4d36 feat(partition): copy the partition GUID into the partition structure
Copy the UniquePartitionGUID member of a GPT partition entry into the
partition_entry structure. This GUID is subsequently used to identify
the image to boot on a platform which supports multiple partitions of
firmware components using the FWU metadata structure.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I8b55a1ee7deb1353886fbd8ebde53055d677fee0
2022-01-27 18:09:02 +05:30
Madhukar Pappireddy 0b1cfc2988 Merge "fix(st-ddr): add missing debug.h" into integration 2022-01-27 02:01:32 +01:00
Maninder Singh e3a234971a fix(nxp-drivers): ddr: corrects mapping of HNFs nodes
Corrects mapping of HNFs nodes with SNFs nodes based on their
proximity in CCN508 ring when disabling unused ddr controller.

When DDRC 2 disabled and DDR 1 is active the mapping is 0x3/3/8/8/8/8/3/3.
When DDRC 1 is disabled and DDR2 is active the mapping is 0x
18/18/13/13/13/13/18/18 .

Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: JaiPrakash Singh <JaiPrakash.singh@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6ec1e02f8ad7e8bb8628913625ff5313a054dcc6
2022-01-26 10:19:08 +08:00
Sandrine Bailleux b19630037d Merge changes from topic "decouple-tb-mb" into integration
* changes:
  refactor(renesas): disable CRYPTO_SUPPORT option
  refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot
  refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
  build: introduce CRYPTO_SUPPORT build option
2022-01-25 08:10:58 +01:00
Manish Pandey b57d9d6f29 Merge changes from topic "new_ls1043a" into integration
* changes:
  docs(maintainers): update nxp layerscape maintainers
  docs(plat/nxp/layerscape): add ls1043a soc and board support
  feat(plat/nxp/ls1043ardb): add ls1043ardb board support
  feat(plat/nxp/ls1043a): add ls1043a soc support
  refactor(plat/ls1043): remove old implementation for platform ls1043
  feat(nxp/driver/dcfg): add some macro definition
  fix(nxp/common/setup): increase soc name maximum length
  feat(nxp/common/errata): add SoC erratum a008850
  feat(nxp/driver/tzc380): add tzc380 platform driver support
  feat(tzc380): add sub-region register definition
  feat(nxp/common/io): add ifc nor and nand as io devices
  feat(nxp/driver/ifc_nand): add IFC NAND flash driver
  feat(nxp/driver/ifc_nor): add IFC nor flash driver
  feat(nxp/driver/csu): add bypass bit mask definition
  feat(nxp/driver/dcfg): add gic address align register definition
  feat(nxp/common/rcpm): add RCPM2 registers definition
  fix(nxp/common/setup): fix total dram size checking
  feat(nxp/common): add CORTEX A53 helper functions
2022-01-20 17:29:00 +01:00
Jiafei Pan de9e57ff1f feat(nxp/driver/tzc380): add tzc380 platform driver support
Added TZC380 platform driver support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Id0aa6cb64fa7af79dd44e0dbb0e62cb2fd4cb824
2022-01-20 23:38:03 +08:00
Jiafei Pan 28279cf2c1 feat(nxp/driver/ifc_nand): add IFC NAND flash driver
Support IFC NAND flash as boot device.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I1aba7035ff70b179915e181c04e7b00be2066abe
2022-01-20 23:38:03 +08:00
Jiafei Pan e2fdc77ba4 feat(nxp/driver/ifc_nor): add IFC nor flash driver
Add IFC Nor flash driver.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3275664b8848d0fe3c15ed92d95fb19adbf57f84
2022-01-20 23:38:03 +08:00
Yann Gautier 15ca2c5e14 fix(st-ddr): add missing debug.h
In a later patch, the stm32mp1_def.h will be reworked. The inclusion
of common/debug.h may not be done there through another included file.
Add this header inclusion in the files that need it.

Change-Id: I83687f7910032ca38c0856796580a650e1e41a68
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-19 15:13:18 +01:00
Yann Gautier 44fb470b7f fix(st-clock): correct types in error messages
Replace wrong %d with the correct types.
This issue was found with the compilation flag:
-Wformat-signedness

Change-Id: Iec3817a245f964ce444b59561b777ce06c51a60a
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2022-01-18 18:39:52 +01:00
Gabriel Fernandez b208e3da04 refactor(st-clock): directly use oscillator name
Instead of transmitting an 'enum stm32mp_osc_id', just send
directly the clock name with a 'const char *'

Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7b1d35fc932
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2022-01-18 18:39:52 +01:00
Lionel Debieve 31e9750bc1 feat(st-clock): check HSE configuration in serial boot
In case of programmer mode, the bootrom manages to auto-detect
HSE clock configuration. In order to detect a bad device tree
setting in BL2, it will crash during programming if the configuration
is not aligned with the auto-detection.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I230697695745d6282d14b1ebfa6e4c4caa0cd8e2
2022-01-18 17:07:41 +01:00
Patrick Delaunay bcccdacc7e feat(st-clock): manage disabled oscillator
Support "disabled" status for oscillator in device tree.

At boot time, the clock tree initialization performs the following
tasks:
- enabling of the oscillators present in the device tree and not
  disabled,
- disabling of the HSI oscillator if the node is absent or disabled
  (always activated by bootROM).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I176276022334f3d97ba0250b54062f0ae970e239
2022-01-18 17:06:13 +01:00
Nicolas Le Bayon 964e5ff184 refactor(st-clock): improve DT parsing for PLL nodes
Add a function to get PLL settings from DT:
"cfg" property is mandatory, an error is generated if not found.
"frac" is optional, default value is returned if not found.
"csg" is optional too, a boolean value indicates if it has been
found, and its value is updated.

Store each PLL node validity information, this avoids parsing DT
several times.

Change-Id: I039466fbe1e67d160f7112814e7bb63b661804d0
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2022-01-18 17:03:45 +01:00
Manish V Badarkhe 0aa0b3afd6 refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
Measured-Boot and Trusted-Boot are orthogonal to each other and hence
removed dependency of Trusted-Boot on Measured-Boot by making below
changes -
1. BL1 and BL2 main functions are used for initializing Crypto module
   instead of the authentication module
2. Updated Crypto module registration macro for MEASURED_BOOT with only
   necessary callbacks for calculating image hashes
3. The 'load_auth_image' function is now used for the image measurement
   during Trusted or Non-Trusted Boot flow

Change-Id: I3570e80bae8ce8f5b58d84bd955aa43e925d9fff
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-01-11 23:06:22 +00:00
Manish Pandey f7a92518f6 Merge changes from topic "st_ddr_updates" into integration
* changes:
  refactor(st-ddr): move basic tests in a dedicated file
  refactor(st-ddr): reorganize generic and specific elements
  feat(stm32mp1): allow configuration of DDR AXI ports number
  refactor(st-ddr): update parameter array initialization
  feat(st-ddr): add read valid training support
  refactor(stm32mp1): remove the support of calibration result
  fix(st-ddr): correct DDR warnings
2022-01-07 17:24:54 +01:00
Manish Pandey 5b0962833a Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration
* changes:
  feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3
  feat(plat/rcar3): modify type for Internal function argument
  feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
  fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53
2022-01-05 17:28:13 +01:00
Manish Pandey f8183f4df1 Merge "fix(ufs): delete call to inv_dcache_range for utrd" into integration 2022-01-05 12:08:14 +01:00
Nicolas Le Bayon 63d2159846 refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.

Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
2022-01-05 11:47:46 +01:00
Nicolas Le Bayon 06e55dc842 refactor(st-ddr): reorganize generic and specific elements
stm32mp_ddrctl structure contains DDRCTRL registers definitions.
stm32mp_ddr_info contains general DDR information extracted from DT.
stm32mp_ddr_size moves to the generic side.
stm32mp1_ddr_priv contains platform private data.

stm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to
retrieve data from DT. They are located in new generic c/h files in
which stm32mp_ddr_param structure is declared. Platform makefile
is updated.

Adapt driver with this new classification.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I4187376c9fff1a30e7a94407d188391547107997
2022-01-05 11:09:59 +01:00
Yann Gautier 88f4fb8fa7 feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.

Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-05 11:09:59 +01:00
Yann Gautier ba7d2e2698 refactor(st-ddr): update parameter array initialization
Force alignment of the size of parameters array with the expected
value by the binding.
The registers dynamic structs are removed as not used in TF-A.

Change-Id: I7a41f355a435f54fbf23f468cca87c7f8f7e69e8
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-05 11:09:59 +01:00
Nicolas Le Bayon 5def13eb01 feat(st-ddr): add read valid training support
Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2
2022-01-05 11:09:59 +01:00
Patrick Delaunay 26cf5cf6d6 refactor(stm32mp1): remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.

The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.

This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
  the optional "st,phy-cal"

After this patch the built-in calibration is always executed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
2022-01-05 11:09:59 +01:00
Yann Gautier a078134e23 fix(st-ddr): correct DDR warnings
Replace %d with %u in logs, to avoid warning when
-Wformat-signedness is enabled.
And correct the order of includes.

Change-Id: I7c711a37fc1deceb8853831a8a09ae50422859c9
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2022-01-05 09:19:05 +01:00
Yann Gautier d50e7a71cb fix(st-sdmmc2): check regulator enable/disable return
The issue was reported by Coverity [1]. The return of the functions
regulator_disable() and regulator_enable() was not checked.
If they fail, this means there is an issue either with PMIC or I2C.
The board should the stop booting with a panic().

[1] https://scan4.scan.coverity.com/reports.htm#v47771/p11439/mergedDefectId=374565

Change-Id: If5dfd5643c210e03ae4b1f4cab0168c0db89f60e
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-04 15:25:04 +01:00
André Przywara e752fa4a4c Merge "feat(allwinner): allow to skip PMIC regulator setup" into integration 2022-01-01 02:16:14 +01:00
Wing Li c5ee8588bf fix(ufs): delete call to inv_dcache_range for utrd
The utrd struct is allocated on the stack by ufs_check_resp's caller.
Invalidating the utrd struct is unnecessary since it's only read from,
and can cause other values stored on the stack (e.g. link register) to
be inadvertently invalidated.

Change-Id: Icd455b52beb2677fafc083d68d0bfa0645b7194b
Signed-off-by: Wing Li <wingers@google.com>
2021-12-28 10:41:14 -08:00
Andre Przywara 67412e4d7a feat(allwinner): allow to skip PMIC regulator setup
For somewhat historical reasons we are doing some initial PMIC regulator
setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked
fine so far, but there is at least one board (OrangePi 3) that gets upset,
because the Ethernet PHY needs some *coordinated* bringup of *two*
regulators.

To avoid custom hacks, let's introduce a build option to keep doing the
regulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break
support for some devices on some boards in U-Boot (Ethernet and HDMI),
but will allow to bring up the OrangePi 3 in Linux correctly. We keep
the default at 1 to not change the behaviour for all other boards.

After U-Boot gained proper PMIC support at some point in the future, we
will probably change the default to 0, to get rid of the less optimal
PMIC code in TF-A.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7
2021-12-27 15:32:22 +00:00
Madhukar Pappireddy 93b153b5bf Merge changes from topic "st_regulator" into integration
* changes:
  feat(st-sdmmc2): manage cards power cycle
  feat(stm32mp1): register fixed regulator
  feat(st-drivers): introduce fixed regulator driver
  refactor(st): update CPU and VDD voltage get
  refactor(stm32mp1-fdts): update regulator description
  refactor(st-pmic): use regulator framework for DDR init
  feat(st-pmic): register the PMIC to regulator framework
  refactor(st-pmic): split initialize_pmic()
  feat(stm32mp1): add regulator framework compilation
  feat(regulator): add a regulator framework
  feat(stpmic1): add new services
  feat(stpmic1): add USB OTG regulators
  refactor(st-pmic): improve driver usage
  refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean
  refactor(stm32mp1): re-order drivers init
2021-12-24 00:13:50 +01:00
Yann Gautier 258bef913a feat(st-sdmmc2): manage cards power cycle
To correctly initialize the MMC devices, a power cycle is required.
For this we need to:
- disable vmmc-supply regulator
- make the power cycle required for SDMMC2 peripheral
- enable regulators

Change-Id: I2be6d9082d1cc4c864a82cf2c31ff8522e2d31a2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet 5d6a2646f7 feat(st-drivers): introduce fixed regulator driver
Fixed regulator is mainly used when no pmic is available

Change-Id: Ib6a998684bcb055ba95a093bee563372d9051474
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet 0ba71ac901 refactor(st-pmic): use regulator framework for DDR init
Use regulator framework for DDR initialization.

Change-Id: I9dffe499ca12cdc35904de7daf2dda821b267a31
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier 85fb175b5e feat(st-pmic): register the PMIC to regulator framework
Register the PMIC to the regulator framework.

Change-Id: Ic825a8ef08505316db3dbd5944d62ea907f73c4a
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Nicolas Le Bayon ae7792e058 refactor(st-pmic): split initialize_pmic()
print_pmic_info_and_debug() prints the PMIC version ID and displays
regulator information if debug is enabled.
It is under DEBUG flag and called after initialize_pmic() in BL2.

Change-Id: Ib81a625740b7ec6abb49cfca05e44c69efaa4718
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet d5b4a2c4e7 feat(regulator): add a regulator framework
Add a regulator framework to:
- provide an interface to consumers and drivers,
- connect consumers with drivers,
- handle most of devicetree-parsing,
- handle always-on and boot-on regulators,
- handle min/max voltages,

Change-Id: I23c939fdef2c71a416c44c9de332f70db0d2aa53
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet ea552bf5a5 feat(stpmic1): add new services
Add support for ICC, sink mode, bypass mode,
active discharge and list voltages.
Handle LDO3 sink source mode in a different way to avoid
setting voltage while in sink source mode.

Change-Id: Ib1b909fd8a153f542917f650e43e24317a570534
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2021-12-22 14:04:32 +01:00
Etienne Carriere 13fbfe046e feat(stpmic1): add USB OTG regulators
Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to
USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are
needed since manipulated during the suspend/resume power sequence
as per FDT description for stm32mp15x-xxx boards from
STMicroelectronics.

Change-Id: I6217de707e49882bd5a9100db43e0d354908800d
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2021-12-22 14:04:32 +01:00
Nicolas Le Bayon c77c7d9e30 refactor(st-pmic): improve driver usage
Store status of dt_pmic_status() as local static variable,
this avoids parsing DT several times.
In the same way, store nodes in dt_pmic_i2c_config() and
in dt_get_pmic_node() as local static variables.

Change-Id: I4585e9dfdde2847a369bffcc6f2b39ecc2b74de1
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2021-12-22 14:04:32 +01:00
Nicolas Le Bayon 16e56a75de refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean
Improve use and readability.

Change-Id: Ia99fc38287f36c9dd12bfe51352afa5da68c0e47
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier 33667d299b feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().

Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2021-12-22 13:08:09 +01:00