This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.
Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch adds macros, to define registers required to support GPU
reset, for Tegra194 SoCs.
Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The polarity
for the bit was incorrect in the previous check.
Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.
For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.
Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers are locked and TZDRAM setup has already been done by the
previous bootloaders, before setting up the fence.
Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.
The Tegra194 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.
Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.
Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch cleans up all references to the Tegra186 family of SoCs.
Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds the driver, to implement the programming sequence to
save/restore hardware context, during System Suspend/Resume.
Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Jeff Tsai <jefft@nvidia.com>
This patch renames all the secure scratch registers to reflect
their usage.
This is a list of all the macros being renamed:
- SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_*
Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39
Signed-off-by: Steven Kao <skao@nvidia.com>
Main fixes:
Fix invalid use of function pointer [Rule 1.3]
Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
convert object type to match the type of function parameters
[Rule 10.3]
Force operands of an operator to the same type category [Rule 10.4]
Fix implicit widening of composite assignment [Rule 10.6]
Fixed if statement conditional to be essentially boolean [Rule 14.4]
Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
Voided non c-library functions whose return types are not used
[Rule 17.7]
Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
There is a possibility that once we have checked that the GPU is
in reset, some component can get still it out of reset.
This patch removes the check register macro.
Change-Id: Idbbba36f97e37c7db64ab9e42848a040ccd05acd
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch adds MC registers and macros to allow CPU to access
TZRAM.
Change-Id: I46da526aa760c89714f8898591981bb6cfb29237
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch corrects the TEGRA_CAR_RESET_BASE macro value to
0x20000000 from 0x200000000.
Change-Id: Iba25394ea99237df85395c39059926c5a8b26a84
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch adds masks for the TZDRAM base/size registers.
Change-Id: I5f688793be8cace28d2aa2d177a295e4faffd666
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
T194 XUSB has support for XUSB virtualization. It will have one
physical function (PF) and four Virtual function (VF)
There were below two SIDs for XUSB until T186.
1) #define TEGRA_SID_XUSB_HOST 0x1bU
2) #define TEGRA_SID_XUSB_DEV 0x1cU
We have below four new SIDs added for VF(s)
3) #define TEGRA_SID_XUSB_VF0 0x5dU
4) #define TEGRA_SID_XUSB_VF1 0x5eU
5) #define TEGRA_SID_XUSB_VF2 0x5fU
6) #define TEGRA_SID_XUSB_VF3 0x60U
When virtualization is enabled then we have to disable SID override
and program above SIDs in below newly added SID registers in XUSB
PADCTL MMIO space. These registers are TZ protected and so need to
be done in ATF.
a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
This change disables SID override and programs XUSB SIDs in
above registers to support both virtualization and non-virtualization.
Change-Id: I38213a72999e933c44c5392441f91034d3b47a39
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.
Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch changes direct writes to ACTLR_ELx registers to use
read-modify-write instead.
Change-Id: I536dce75c01356ce054dd2edee80875e56164439
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch adds platform support for the Memory Controller and
SMMU drivers, for the Tegra194 SoC.
Change-Id: Id8b482de70f1f93bedbca8d124575c39b469927f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds macros to check the GPU reset status bit, before
resizing the VideoMem region.
Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds macros defining the generalised security carveout
registers. These macros help us program the TZRAM carveout access
and the Video Protect Clear carveout access.
Change-Id: I8f7b24b653fdb702fb57a4097801cb3eae050294
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch defines the macro for the TEGRA_TMRUS aperture size.
Change-Id: I33fb674c6a7be8d02971667e7bf8650b7adc62ef
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch adds support for all three SMMU devices present on the SoC.
The following changes have been done:
Add SMMU devices to the memory map
Update register read and write functions
Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.
Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Pritesh Raithatha
Steven Kao
Jeetesh Burman
Varun Wadekar
Anthony Zhou
Harvey Hsieh
Ajay Gupta