Commit Graph

8212 Commits

Author SHA1 Message Date
Rajan Vaja 1ba2d84fe2 xilinx: versal: Updated Response of QueryData API call
For the current XilPM calls, The handler of IPI returns information
with 16 Bytes data.
So during QueryData API call for the ClockName and PinFunctionName,
response data(name of clock or function) response[0..3] are used to
return name. And status is not being returned for such API.

Updated XilPM calls reply in a consistent way and The handler of IPI
return information with 32Bytes data. Where response[0] always set
to status.
For the version-2 of QueryData API, during call for the ClockName
and PinFunctionName, response data(name of clock or function) get as
response[1...4].

To support both the version of QueryData API, added version based
compatibility by the use of feature check.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I336128bff7bbe659903b0f8ce20ae6da7e3b51b4
2020-12-07 11:09:56 +00:00
Venkatesh Yadav Abbarapu abf27efac6 plat:xilinx:versal: Use defaults when PDI is without sw partitions
In JTAG mode check the ATF handoff structure, if the magic string
is not present then use bl32 and bl33 default values.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I1f2c4a2060d8a2e70d3b5fb2473124b685f257fc
2020-12-07 11:09:47 +00:00
Ravi Patel addc4e969b plat: xilinx: Mask unnecessary bytes of return error code
Versal firmware adds extra error codes along with PM error codes
while sending response to driver. This makes incorrect error
identification at driver side.

To fix this, mask the unnecessary error bytes before sending the
error code to the driver.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I18c2f3bd2d067e91344852c2f0c1bafea0e6eb23
2020-12-07 11:08:09 +00:00
Ravi Patel d4c7b55050 xilinx: versal: Skip store/restore of GIC during CPU idle
GIC registers needs to be stored/restored during system
suspend/resume only and not during CPU idle.
During CPU idle, minimum 1 CPU is in ON state.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I5de2ce3a61bf4260f9385349202b0f592a47aaba
2020-12-07 11:07:41 +00:00
Venkatesh Yadav Abbarapu 4b8ab607ea plat: versal: Update API list in feature check
Add below API in feature check list which is actually present in
firmware:
- PM_GET_CHIPID

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I98b82da74164f065c8835861f74b0f2855e9bcbf
2020-12-07 11:07:32 +00:00
Ravi Patel b05d2792ae xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
Existing code passes ACPU0 to LibPM as node_id in set_wakeup_source()
call because last suspending core will be ACPU0 in most of the case.

Now it may be possible that user may disable the ACPU0 using hot-plug
and after that it suspends Linux. So in that case ACPU0 will not be
last suspending core.

To overcome above scenario, pass the current running processor ID
while calling set_wakeup_source().

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If15354c2150b5bb1305b5f93ca4e8c7a81d59f0a
2020-12-07 11:07:24 +00:00
Pali Rohár e33370828d plat: marvell: armada: a3k: Simplify check if WTP variable is defined
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ieb352f0765882efdcb64ef54e6b2a39768590a06
2020-12-07 11:06:36 +00:00
Pali Rohár bc1f368743 plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
These two targets are build by make subprocesses and are independent.
So splitting them into own targets allow make to build them in parallel.
$(TIMBUILD) script depends on $(TIMDDRTOOL) so specify it in Makefile.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I139fc7fe64d8de275b01a853e15bfb88c4ff840d
2020-12-07 11:06:13 +00:00
Pali Rohár 23b1be79d7 plat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB
Add check when building mrvl_bootimage that size of bl1 image is not bigger
than maximal size.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib873debd3cfdba9acd4c168ee37edab3032e9f25
2020-12-07 11:05:53 +00:00
Pali Rohár e4bbd39c65 plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
FORCE target is used as a dependency for other file targets which needs to
be always rebuilt. .PHONY target is standard Makefile target which specify
non-file targets and therefore needs to be always rebuilt.

Targets clean, realclean and distclean are .PHONY targets used to remove
built files. Correctly set that mrvl_clean target is prerequisite for these
clean targets to ensure that built files are removed.

Finally this change with usage of FORCE target allows to remove mrvl_clean
hack from the prerequisites of a8k ${DOIMAGETOOL} target which was used
just to ensure that ${DOIMAGETOOL} is always rebuilt via make subprocess.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2fa8971244b43f101d846fc433ef7b0b6f139c92
2020-12-07 11:05:27 +00:00
Pali Rohár ed9bae6ad5 plat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT) code
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id766db4a900a56c795fe5ffdd8a2b80b1aaa2132
2020-12-07 11:05:20 +00:00
Pali Rohár bafc9476b9 plat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iaecd6c24bf334a959ac2bf395c3ee49c810b01a7
2020-12-07 11:05:14 +00:00
Pali Rohár 2f852b89b1 plat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF-A repository
Create copy of WTMI images instead of moving them into TF-A build directory.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2dc24c33b9ce540e4acde51fc1a5c946ae66a5d7
2020-12-07 11:05:09 +00:00
Pali Rohár 13aa895623 plat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG)
Rather create a temporary copy in $(BUILD_PLAT) and modify only copy.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I256c029106ea6f69faa086fc4e5bee9f68cd257f
2020-12-07 11:05:04 +00:00
Pali Rohár bdcd1bd0a5 plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)
$(WTMI_IMG) is used only by $(MAKE) subprocess in $(DOIMAGEPATH) directory.
So calling truncate on $(WTMI_IMG) after $(MAKE) in $(DOIMAGEPATH) has no
effect and can just damage input file for future usage. Therefore remove
this truncate call.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I9925c54c5d3d10eadc19825c5565ad4598a739a7
2020-12-07 11:04:58 +00:00
Venkatesh Yadav Abbarapu 490d81d2fa plat: xilinx: zynqmp: Enable log messages for debug
Save some space by enabling the log messages like bl33 address
only for debug builds. Also check the bl33 and bl32 address and
print only if this is not NULL.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I58d846bf69a75e839eb49abcbb9920af13296886
2020-12-06 21:46:24 -08:00
Tejas Patel a7379a2ab1 plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG
For boot health status PMU Global General Storage Register 4 is
used. GGS4 can be used for other purpose along with boot health
status. So, change its name from PM_BOOT_HEALTH_STATUS_REG
to PMU_GLOBAL_GEN_STORAGE4.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I2f5c4c6a161121e7cdb4b9f0f8711d0dad16c372
2020-12-06 21:46:03 -08:00
Madhukar Pappireddy 7fc19b8ea9 Merge "qemu/qemu_sbsa: increase SHARED_RAM_SIZE" into integration 2020-12-07 03:40:39 +00:00
Madhukar Pappireddy 307f3b90c7 Merge "plat: xilinx: zynqmp: Include GICv2 makefile" into integration 2020-12-05 23:28:25 +00:00
Venkatesh Yadav Abbarapu 84f2e34fee plat: xilinx: zynqmp: Include GICv2 makefile
Update the xilinx platform makefile to include GICv2 makefile
instead of adding the individual files. Updating this change
as per the latest changes done in the commit #1322dc94f7.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I79d8374c47a7f42761d121522b32ac7a5021ede8
2020-12-03 20:30:37 -07:00
Madhukar Pappireddy 79df6ea430 Merge "plat: xilinx: Use fno-jump-tables flag in CPPFLAGS" into integration 2020-12-03 16:58:59 +00:00
Manish Pandey 49462851aa Merge ".editorconfig: set max line length to 100" into integration 2020-12-03 16:14:40 +00:00
Madhukar Pappireddy 5e5c399de0 Merge "plat: marvell: Update SUBVERSION to match Marvell's forked version" into integration 2020-12-03 15:51:50 +00:00
Yann Gautier 279f77b492 .editorconfig: set max line length to 100
Relax the 80 character line length, as done in checkpatch,
since Linux 5.7.

Change-Id: I093a2e6a45336339193173f7ff6a461279cf411d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-12-03 15:39:23 +00:00
Manish Pandey 99ddfc0e46 Merge "Aarch64: Add support for FEAT_PANx extensions" into integration 2020-12-03 13:08:02 +00:00
Olivier Deprez 5e8911a035 Merge "Aarch64: Add support for FEAT_MTE3" into integration 2020-12-03 11:02:26 +00:00
Madhukar Pappireddy 0888694076 Merge "rockchip: Add support for the stack protector" into integration 2020-12-02 18:26:47 +00:00
Alexei Fedorov 0563ab08e8 Aarch64: Add support for FEAT_MTE3
This patch provides the following changes:
- Adds definition for FEAT_MTE3 value in ID_AA64PFR1_EL1 register
- Enables Memory Tagging Extension for FEAT_MTE3.

Change-Id: I735988575466fdc083892ec12c1aee89b5faa472
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-12-02 13:53:03 +00:00
Manish Pandey 91cc872c64 Merge "Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms" into integration 2020-12-02 12:18:02 +00:00
Lauren Wehrmeister 9dd2896e65 Merge "Add support for Neoverse-N2 CPUs." into integration 2020-12-01 17:06:46 +00:00
Masato Fukumori 54b590ec0d qemu/qemu_sbsa: increase SHARED_RAM_SIZE
Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB.

sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If
qemu is configured with 512 cpus, region size used by qemu is greater
than 4KB.

Signed-off-by: Masato Fukumori <masato.fukumori@linaro.org>
Change-Id: I639e44e89335249d385cdc339350f509e9bd5e36
2020-12-01 14:01:24 +00:00
Christoph Müllner 826ba363c4 rockchip: Add support for the stack protector
It uses the system timer as "entropy" source in the same
way as QEMU, layerscape and others.

Change-Id: Icda17b78e85255bea96109ca2ee0e091187d62ac
Signed-off-by: Christoph Müllner <christophm30@gmail.com>
2020-12-01 11:54:57 +01:00
Javier Almansa Sobrino 25bbbd2d63 Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
2020-11-30 19:12:56 +00:00
Alexei Fedorov a83103c824 Aarch64: Add support for FEAT_PANx extensions
This patch provides the changes listed below:
- Adds new bit fields definitions for SCTLR_EL1/2 registers
- Corrects the name of SCTLR_EL1/2.[20] bit field from
SCTLR_UWXN_BIT to SCTLR_TSCXT_BIT
- Adds FEAT_PANx bit field definitions and their possible
values for ID_AA64MMFR1_EL1 register.
- Adds setting of SCTLR_EL1.SPAN bit to preserve PSTATE.PAN
on taking an exception to EL1 in spm_sp_setup() function
(services\std_svc\spm_mm\spm_mm_setup.c)

Change-Id: If51f20e7995c649126a7728a4d0867041fdade19
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-11-30 15:24:52 +00:00
Manish Pandey 9acf573621 Merge changes from topic "xilinx-pm-mainline-linux" into integration
* changes:
  zynqmp: pm: update error codes to match Linux and PMU Firmware
  zynqmp: pm: Filter errors related to clock gate permissions
2020-11-30 12:05:11 +00:00
Manish Pandey 441e7f489f Merge "mediatek: mt8183: add timer V20 compensation" into integration 2020-11-27 11:11:39 +00:00
Manish Pandey 38f7e32eac Merge changes I5ad52909,Iea3214a2 into integration
* changes:
  fdts: Add VirtIO network device to Morello FVP
  fdts: Remove "virtio-rng" from Morello FVP
2020-11-24 12:04:42 +00:00
Manish Pandey 9272a8fd7b Merge "plat:qti Mandate SMC implementaion" into integration 2020-11-23 10:29:48 +00:00
Jessica Clarke de7091a1f5 fdts: Add VirtIO network device to Morello FVP
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: I5ad5290925f637b94168b507b3dcbdd5e1b82e5a
2020-11-23 09:35:39 +05:30
Jessica Clarke 5c336e0636 fdts: Remove "virtio-rng" from Morello FVP
This is not a standard string that any kernel recognises, nor do any of
the FDTs embedded in kernels specify this, nor does QEMU's virt machine.
Whilst its presence does no harm, it's not a thing code should consult
as a result, and so drop it in order to not cause confusion and risk
incorrect code being written to search for it.

Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: Iea3214a23181c54e600cf8f4f12dfc822140c23d
2020-11-23 09:35:21 +05:30
Madhukar Pappireddy 7cf307d209 Merge "plat/nvidia: tegra: Rename SMC API" into integration 2020-11-20 15:36:37 +00:00
Manish Pandey a68626070e Merge "plat/qemu_sbsa: Include libraries for Cortex-A72" into integration 2020-11-20 12:30:10 +00:00
Tanmay Jagdale 5f14ca9937 plat/qemu_sbsa: Include libraries for Cortex-A72
Include libraries needed to emulate Cortex-A72 on
sbsa-ref target of QEMU.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Change-Id: I98cf17b1662c70898977a841af07e07b5cfca8ba
2020-11-20 16:39:49 +05:30
Manish V Badarkhe 840fa94aa3 plat/nvidia: tegra: Rename SMC API
Renamed SMC API from "plat_smccc_feature_available" to
"plat_is_smccc_feature_available" as per the current implementation.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib0fa400816fba61039c2029a9e127501a6a36811
2020-11-19 20:09:28 +00:00
Saurabh Gorecha 7a0f795ee7 plat:qti Mandate SMC implementaion
renamed smcc api with correct name  plat_is_smccc_feature_available

Change-Id: I277ece02bffc2caa065256576c1a047dfcde1c92
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
2020-11-20 01:09:52 +05:30
Manish Pandey 20c378920e Merge changes from topic "mrvl_bootimage" into integration
* changes:
  docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes
  plat: marvell: armada: Add new target mrvl_bootimage
  plat: marvell: armada: a3k: Add support for building $(DOIMAGETOOL)
2020-11-19 11:18:26 +00:00
Pali Rohár d22db1b050 plat: marvell: Update SUBVERSION to match Marvell's forked version
Marvell's TF-A fork has SUBVERSION set to devel-18.12.2.

The only differences between Marvell's devel-18.12.0 and devel-18.12.2
versions are documentation updates and cherry-picked patches from TF-A
upstream repository.

So upstream TF-A has already all changes from Marvell's TF-A devel-18.12.2
fork and therefore update SUBVERSION to reflect this state.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ce946a5176a5cbf124acd8037392463d586b072
2020-11-19 10:17:39 +00:00
Pali Rohár f20cb7e54e docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes
Also add example how to build TF-A for A3720 Turris MOX board and also fix
style/indentation issues and information about default values.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2dc957307b1b627b403a8d960e85f5ac9e15aee5
2020-11-19 10:17:33 +00:00
Pali Rohár 91bc2da73c plat: marvell: armada: Add new target mrvl_bootimage
This new target builds boot-image.bin binary as described in documentation.
This image does not contain WTMI image and therefore WTP repository is not
required for building.

Having ability to build just this boot-image.bin binary without full
flash-image.bin is useful for A3720 Turris MOX board which does not use
Marvell's WTP and a3700_utils.

To reduce duplicity between a8k and a3k code, define this new target and
also definitions for $(BUILD_PLAT)/$(BOOT_IMAGE) in common include file
marvell_common.mk.

For this purpose it is needed to include plat/marvell/marvell.mk file from
a3700_common.mk unconditionally (and not only when WTP is defined). Now
when common file plat/marvell/marvell.mk does not contain definition for
building $(DOIMAGETOOL), it is possible to move its inclusion at the top of
the a3700_common.mk file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic58303b37a1601be9a06ff83b7a279cb7cfc8280
2020-11-19 10:17:28 +00:00
Pali Rohár c6a7ab7787 plat: marvell: armada: a3k: Add support for building $(DOIMAGETOOL)
Current binary wtptp/linux/tbb_linux which is specified in $(DOIMAGETOOL)
variable points to external pre-compiled Marvell x86_64 ELF linux binary
from A3700-utils-marvell WTP repository.

It means that currently it is not possible to compile TF-A for A3720 on
other host platform then linux x86_64.

Part of the A3700-utils-marvell WTP repository is also source code of
$(DOIMAGETOOL) TBB_Linux tool.

This change adds support for building $(DOIMAGETOOL) also for a3k platform.

After running $(MAKE) at appropriate subdirectory of A3700-utils-marvell
WTP repository, compiled TBB_linux tool will appear in WTP subdirectory
wtptp/src/TBB_Linux/release/. So update also $(DOIMAGETOOL) variable to
point to the correct location where TBB_linux was built.

To build TBB_linux it is required to compile external Crypto++ library
which is available at: https://github.com/weidai11/cryptopp.git

User needs to set CRYPTOPP_PATH option to specify path to that library.

After this change it is now possible to build whole firmware for A3720
platform without requirement to use pre-compiled/proprietary x86_64
executable binaries from Marvell.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6f26bd4356778a2f8f730a223067a2e550e6c8e0
2020-11-19 10:17:21 +00:00