Commit Graph

8212 Commits

Author SHA1 Message Date
Alexei Fedorov 47f2445ad6 Plat AXG: Fix PLAT_MAX_PWR_LVL value
This patch fixes AXG platform build error:
plat/amlogic/axg/axg_pm.c: In function 'axg_pwr_domain_off':
plat/amlogic/axg/axg_pm.c:124:43: error: array subscript 2
 is above array bounds of 'const plat_local_state_t[2]'
 {aka 'const unsigned char[2]'}
by changing PLAT_MAX_PWR_LVL from MPIDR_AFFLVL1 to MPIDR_AFFLVL2
in plat\amlogic\axg\include\platform_def.h.

Change-Id: I9a701e8f26231e62f844920aec5830664f3fb324
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-12-29 13:52:11 +00:00
Madhukar Pappireddy 2773536b17 Merge "plat/arm/rdn2: update gic redistributor base address" into integration 2020-12-16 15:44:59 +00:00
Vijayenthiran Subramaniam fb86e5373c plat/arm/rdn2: update gic redistributor base address
RD-N2 platform has been updated to use six GIC ITS blocks. This results
in change in base address of the GIC Redistributor to accomodate two
new GIC ITS blocks. Update the base address of GICR to reflect the same.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I740a547328fb9a9f25d7a09c08e61bdbc8bf781c
2020-12-16 13:29:37 +05:30
Mark Dykes 29a8814f4e Merge "Add support for FEAT_MTPMU for Armv8.6" into integration 2020-12-15 19:33:40 +00:00
Manish Pandey de15579053 Merge "TF-A: Add build option for Arm Feature Modifiers" into integration 2020-12-11 17:19:14 +00:00
Madhukar Pappireddy bd054fd66b Merge changes from topic "rdevans" into integration
* changes:
  doc: Update list of supported FVP platforms
  board/rdn2: add board support for rdn2 platform
  plat/arm/sgi: adapt to changes in memory map
  plat/arm/sgi: add platform id value for rdn2 platform
  plat/arm/sgi: platform definitions for upcoming platforms
  plat/arm/sgi: refactor header file inclusions
  plat/arm/sgi: refactor the inclusion of memory mapping
2020-12-11 15:21:54 +00:00
Javier Almansa Sobrino 0063dd1708 Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.

If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.

This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
2020-12-11 12:49:20 +00:00
Alexei Fedorov f18217902a TF-A: Add build option for Arm Feature Modifiers
This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults to
'none'. This option translates into compiler option
'-march=armvX[.Y]-a+[no]feature+...'.

Change-Id: I37742f270a898f5d6968e146cbcc04cbf53ef2ad
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-12-10 15:31:51 +00:00
Madhukar Pappireddy 2736aca597 Merge "xilinx: versal: fix static failure" into integration 2020-12-10 14:28:28 +00:00
Manish Pandey a82b5f70fb xilinx: versal: fix static failure
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Icef550072296d6aba89a0827dd72d0b86047556f
2020-12-10 10:48:22 +00:00
Manish Pandey 852e494075 Merge changes from topic "versal-bug-fixes-and-new-apis" into integration
* changes:
  plat: xilinx: versal: Add support of register notifier
  plat: xilinx: versal: Add support to get clock rate value
  plat: xilinx: versal: Add support of set max latency for the device
  plat: versal: Add InitFinalize API call
  xilinx: versal: Updated Response of QueryData API call
  plat:xilinx:versal: Use defaults when PDI is without sw partitions
  plat: xilinx: Mask unnecessary bytes of return error code
  xilinx: versal: Skip store/restore of GIC during CPU idle
  plat: versal: Update API list in feature check
  xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
2020-12-09 22:44:44 +00:00
Olivier Deprez c8e8623676 Merge changes from topic "secure_no_primary" into integration
* changes:
  spm: provide number of vCPUs and VM size for first SP
  spm: remove chosen node from SPMC manifests
  spm: move OP-TEE SP manifest DTS to FVP platform
  spm: update OP-TEE SP manifest with device-regions node
  spm: remove device-memory node from SPMC manifests
2020-12-09 15:08:27 +00:00
Olivier Deprez b4b23c780c Merge "docs: Update the FIP generation process using SP images" into integration 2020-12-09 14:08:06 +00:00
Manish V Badarkhe 745da67b27 docs: Update the FIP generation process using SP images
Updated the documentation for the FIP generation process using
SP images.

Change-Id: I4df7f379f08f33adba6f5c82904291576972e106
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-12-09 11:31:51 +00:00
Aditya Angadi 7b24e48a46 doc: Update list of supported FVP platforms
Updated the list of supported FVP platforms with support for RD-N2 FVP.

Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09 10:44:22 +00:00
Aditya Angadi 34e443e21d board/rdn2: add board support for rdn2 platform
Add the initial board support for RD-N2 platform.

Change-Id: I8325885bf248dd92191d6fc92a2da91c23118f8c
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09 10:44:04 +00:00
Aditya Angadi 6bb9f7a1ab plat/arm/sgi: adapt to changes in memory map
Upcoming RD platforms will have an updated memory map for the various
pheripherals on the system. So, for the newer platforms, handle the
memory mapping and other platform specific functionality separately
from the existing platforms.

Change-Id: Iab1355a4c8ea1f6db4f79fcdd6eed907903b6a18
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09 10:40:26 +00:00
Aditya Angadi 1b19ad6847 plat/arm/sgi: add platform id value for rdn2 platform
In preparation for adding the board support for RD-N2 platform, add
macros to define the platform id and the corresponding SCMI platform
info for the RD-N2 platform.

Change-Id: Ie764ae618732b39e316f7ed080421f5d79adab21
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09 10:40:17 +00:00
Aditya Angadi 284efb16b4 plat/arm/sgi: platform definitions for upcoming platforms
Upcoming RD platforms have changes in the SOC address map from that
of the existing platforms. As a prepartory step to add support for the
upcoming platforms, create platform definitions for those platforms.

Change-Id: Ic5df9fed02c44e65ec260bbb5efc1b8dbd919a56
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09 10:40:08 +00:00
Aditya Angadi 60f995fd98 plat/arm/sgi: refactor header file inclusions
Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support for those upcoming RD platforms, refactor the
header file inclusion to allow newer platforms to use a different
set of platform macros.

Change-Id: Ic80283ddadafaa7f766f300652cb0d4e507efdb6
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09 10:37:11 +00:00
Aditya Angadi db2aeddc79 plat/arm/sgi: refactor the inclusion of memory mapping
Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
usable only for existing platforms and let upcoming platforms define
a different set of mmap entries.

Change-Id: Id1ef0293efe8749c78a99237e78d32573c7233aa
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09 15:12:18 +05:30
Manish Pandey aa47d59d40 Merge "rcar_gen3: drivers: console: Treat log as device memory" into integration 2020-12-08 23:02:36 +00:00
Manish Pandey f0f3d3687b Merge changes from topic "zynqmp-bug-fixes" into integration
* changes:
  zynqmp: pm: Update flags in common clk divisor node
  zynqmp: pm_api_clock: Copy only the valid bytes
2020-12-08 22:53:13 +00:00
Marek Vasut 605767475e rcar_gen3: drivers: console: Treat log as device memory
The BL31 log driver is registered before the xlat tables are initialized,
at that point the log memory is configured as device memory and can only
be accessed with up-to-32bit aligned accesses. Adjust the driver to do
just that.

The memset() call has to be replaced by a loop of 32bit writes to the log,
the memcpy() is trivial to replace with a single 32bit write of the entire
TLOG word. In the end, this even simplifies the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie9152e782e67d93e7236069a294df812e2b873bf
2020-12-08 22:27:13 +00:00
Ravi Patel c8f6253683 zynqmp: pm: Update flags in common clk divisor node
Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.

Example:
 Consider a case of nand_ref clock which has 2 divisor and 1 mux.
 The frequency of mux clock is 1500MHz and default value of div1 and
 div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
 When driver requests 80MHz for nand_ref clock, clock framework will
 adjust the div2 value to 1 (setting div2 value 2 results final clock
 to 50MHz which is more inaccurate compare to 100Mhz) which results
 final clock to 100MHz.
 Ideally the value of div1 and div2 should be updated to 19 and 1
 respectively so that final clock goes to around 78MHz.

This patch fixes above problem by allowing change in div1 value.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
2020-12-08 22:24:44 +00:00
Siva Durga Prasad Paladugu f2afaad071 zynqmp: pm_api_clock: Copy only the valid bytes
This patches copies only the valid part of string and
avoids filling junk at the end.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If23772f31f9cf7f5042e8bfc474fbfe77dcd90e7
2020-12-08 22:24:36 +00:00
Manish Pandey 77990838a4 Merge changes Ibbee37c8,Ic3a13c83,Ib7f2380a,I83b477fd,I284956d4, ... into integration
* changes:
  mediatek: mt8192: dcm: Add mcusys related dcm drivers
  mediatek: mt8192: add ptp3 driver
  mediatek: mt8192: Add SiP service
  mediatek: mt8192: add uart save and restore api
  mediatek: mt8192: modify sys_cirq driver
  mediatek: mt8192: add power-off support
  mediatek: mt8192: add pmic mt6359p driver
  mediatek: mt8192: Initialize delay_timer
  mediatek: mt8192: enable NS access for systimer
  mediatek: mt8192: Add CPU hotplug and MCDI support
  mediatek: mt8192: Add MCDI drivers
  mediatek: mt8192: Add SPMC driver
2020-12-08 16:29:52 +00:00
Olivier Deprez 89832ac9ef spm: provide number of vCPUs and VM size for first SP
The primary VM concept is removed from the SPMC.
Update the SPMC manifests with number of Execution Contexts
and SP workspace size for the first Secure Partition (as it
is done for NWd secondary VMs and other SPs).

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I3b9c52666f7dfe74ab1f7d2148ad0070ee44b54e
2020-12-08 13:35:28 +01:00
Olivier Deprez 5134fcbb47 spm: remove chosen node from SPMC manifests
The chosen node is no longer required as the SPMC implements
a specific boot flow which no longer requires this node.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib566b602a7f83003a1b2d0ba5f6ebf4d8b7a9156
2020-12-08 13:35:28 +01:00
Olivier Deprez 76d22f06dc spm: move OP-TEE SP manifest DTS to FVP platform
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0981c43e2ef8172138f65d95eac7b20f8969394e
2020-12-08 13:35:28 +01:00
Olivier Deprez 3ac8680cbb spm: update OP-TEE SP manifest with device-regions node
Specify peripherals accessed by OP-TEE as a Secure Partition
running as a VM managed by the SPMC.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icf9aae038e2b1b0ce4696f78ff964bfff8a1498c
2020-12-08 13:35:28 +01:00
Olivier Deprez b635d11bcd spm: remove device-memory node from SPMC manifests
The PVM concept is removed from the SPMC so the device-memory
node which is specifying the device memory range for the PVM
is no longer applicable.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: If0cb956e0197028b24ecb78952c66ec454904516
2020-12-08 13:35:28 +01:00
Nina Wu 43d7bbcc6c mediatek: mt8192: dcm: Add mcusys related dcm drivers
1. Add mcusys related dcm drivers
2. Turn on mcusys-related dcm by default

Change-Id: Ibbee37c87cc38e7a6cd7c93c2fc0817aad6dbe95
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
2020-12-07 23:31:19 +00:00
elly.chiang 8709c939d8 mediatek: mt8192: add ptp3 driver
enable PTP3 for protecting sysPi

Signed-off-by: elly.chiang <elly.chiang@mediatek.com>
Change-Id: Ic3a13c8314f829dca8547861b98639d1d9444eb2
2020-12-07 23:31:05 +00:00
Nina Wu 189f038f55 mediatek: mt8192: Add SiP service
Add the basic SiP service

Change-Id: Ib7f2380aab910adf8d33498a79ecd287273907c5
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
2020-12-07 23:30:43 +00:00
Yuchen Huang bb28dc7aea mediatek: mt8192: add uart save and restore api
When system resume, we want to print log as soon as possible.
So we add uart save and restore api, and they will be called
when systtem suspend and resume.

Change-Id: I83b477fd2b39567c9c6b70534ef186993f7053ae
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.com>
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
2020-12-07 23:30:27 +00:00
G.Pangao 49fd68abe4 mediatek: mt8192: modify sys_cirq driver
1.Modify this driver to make it more complete and more standard.
2.And makes this driver available for more IC services.
3.Solve some bugs in the software.

Signed-off-by: G.Pangao <gtk_pangao@mediatek.com>
Change-Id: I284956d47ebbbd550ec93767679181185e442348
2020-12-07 23:30:14 +00:00
Hsin-Hsiung Wang 26f3dbe2d6 mediatek: mt8192: add power-off support
add power-off support

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: If19e99971515a8ae1ac9ae21046e4382adc18a69
2020-12-07 23:29:47 +00:00
Hsin-Hsiung Wang cbd6331beb mediatek: mt8192: add pmic mt6359p driver
add pmic mt6359p driver

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I20f2218f7d2087e8d2bf31258cf92a02e0dab77d
2020-12-07 23:28:48 +00:00
Nina Wu 95cc889488 mediatek: mt8192: Initialize delay_timer
Init delay_timer for the use of delay functions

Change-Id: I35aefd7515bb9259634c8b6bc37d8c74da96e8f1
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
2020-12-07 23:28:33 +00:00
Dehui Sun f3fbacaa9a mediatek: mt8192: enable NS access for systimer
Enable NS access for all systimers.

Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I3693997082a1d6f09fef5a79b6cf5a91be46cb8a
2020-12-07 23:28:05 +00:00
James Liao 82c00c2ff5 mediatek: mt8192: Add CPU hotplug and MCDI support
Implement PSCI platform OPs to support CPU hotplug and MCDI.

Change-Id: I31abfc752b69ac40e70bc9e7a55163eb39776c44
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
2020-12-07 23:27:40 +00:00
James Liao 271d9497dc mediatek: mt8192: Add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.

Change-Id: I5110461e8eef86f8383b45f197ec5cb10dbfeb3e
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
2020-12-07 23:27:19 +00:00
James Liao 3d1e536eea mediatek: mt8192: Add SPMC driver
Add SPMC driver for CPU power on/off.

Change-Id: I526b98d5885855efce019dd09cfd93b8816cbf19
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
2020-12-07 23:26:41 +00:00
Madhukar Pappireddy 0b18d5a5d6 Merge changes from topic "zynqmp-misc-enhancement" into integration
* changes:
  plat: xilinx: zynqmp: Enable log messages for debug
  plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG
2020-12-07 18:13:50 +00:00
Manish Pandey cd6eaab627 Merge changes from topic "marvell-a3k-makefile" into integration
* changes:
  plat: marvell: armada: a3k: Simplify check if WTP variable is defined
  plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
  plat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB
  plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
  plat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT) code
  plat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
  plat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF-A repository
  plat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG)
  plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)
2020-12-07 11:29:46 +00:00
Tejas Patel 6af1228677 plat: xilinx: versal: Add support of register notifier
Add support of register notifier.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I41ef4c63abcc9aee552790b843adb25a5fd0c23e
2020-12-07 11:10:19 +00:00
Tejas Patel b6d7b3e9d6 plat: xilinx: versal: Add support to get clock rate value
Add support to get clock's rate value.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I3ed881053ef323b2ca73e13edd0affda860d381d
2020-12-07 11:10:13 +00:00
Tejas Patel 07d8a5f7dc plat: xilinx: versal: Add support of set max latency for the device
Add support of set max latency, to change in the maximum powerup latency
requirements for a specific device currently used by Subsystem.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I8749886abb1a7884a42c4d156d89c9cd562a5b1a
2020-12-07 11:10:07 +00:00
Ravi Patel 2cc1fa9537 plat: versal: Add InitFinalize API call
Add support to call InitFinalize API in Versal which calls
corresponding LibPM API.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I3428b7245b4db1ef6db8a90b7ad20b6e484ed3b2
2020-12-07 11:10:01 +00:00