Commit Graph

8212 Commits

Author SHA1 Message Date
Madhukar Pappireddy 7b12a8d673 Merge "Revert workaround for A77 erratum 1800714" into integration 2020-11-19 01:30:49 +00:00
Madhukar Pappireddy b9ad2bb83e Merge "Revert workaround for A76 erratum 1800710" into integration 2020-11-19 01:30:42 +00:00
Madhukar Pappireddy 7096a45ae0 Merge "Fix typos and misspellings" into integration 2020-11-19 00:31:29 +00:00
Madhukar Pappireddy 730495c7c5 Merge "TSP: Fix GCC 11.0.0 compilation error." into integration 2020-11-18 18:14:14 +00:00
Manish Pandey e2c509a39c Merge "Makefile: Update the minor version to indicate 2.4 release" into integration 2020-11-17 16:43:51 +00:00
Manish V Badarkhe 5edddf3a0f Makefile: Update the minor version to indicate 2.4 release
Updated the minor version to '4' to indicate 2.4 release

Change-Id: Ib142fa15baeb43025fae371c7649199b8121c18f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-11-17 16:06:49 +00:00
Joanna Farley 5ca9754a63 Merge "docs: Update changelog for v2.4 release" into integration 2020-11-17 14:32:01 +00:00
Chris Kay 0bd1a2e94d docs: Update changelog for v2.4 release
Change-Id: I67c9db2fc6d4b83fec2d001745b9305102d4a2ae
Signed-off-by: Chris Kay <chris.kay@arm.com>
2020-11-17 11:49:03 +00:00
Alexei Fedorov caff3c8724 TSP: Fix GCC 11.0.0 compilation error.
This patch fixes the following compilation error
reported by aarch64-none-elf-gcc 11.0.0:

bl32/tsp/tsp_main.c: In function 'tsp_smc_handler':
bl32/tsp/tsp_main.c:393:9: error: 'tsp_get_magic'
 accessing 32 bytes in a region of size 16
 [-Werror=stringop-overflow=]
  393 |         tsp_get_magic(service_args);
      |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~
bl32/tsp/tsp_main.c:393:9: note: referencing argument 1
 of type 'uint64_t *' {aka 'long long unsigned int *'}
In file included from bl32/tsp/tsp_main.c:19:
bl32/tsp/tsp_private.h:64:6: note: in a call to function 'tsp_get_magic'
   64 | void tsp_get_magic(uint64_t args[4]);
      |      ^~~~~~~~~~~~~

by changing declaration of tsp_get_magic function from
void tsp_get_magic(uint64_t args[4]);
to
uint128_t tsp_get_magic(void);
which returns arguments directly in x0 and x1 registers.

In bl32\tsp\tsp_main.c the current tsp_smc_handler()
implementation calls tsp_get_magic(service_args);
, where service_args array is declared as
uint64_t service_args[2];
and tsp_get_magic() in bl32\tsp\aarch64\tsp_request.S
copies only 2 registers in output buffer:
	/* Store returned arguments to the array */
	stp	x0, x1, [x4, #0]

Change-Id: Ib34759fc5d7bb803e6c734540d91ea278270b330
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-11-13 18:47:58 +00:00
johpow01 9bbc03a6e0 Revert workaround for A77 erratum 1800714
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
2020-11-12 14:15:41 -06:00
johpow01 95ed9a9e0d Revert workaround for A76 erratum 1800710
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
2020-11-12 13:55:43 -06:00
David Horstmann 5d9101b39c Fix typos and misspellings
Fix a number of typos and misspellings in TF-A
documentation and comments.

Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: I34c5a28c3af15f28d1ccada4d9866aee6af136ee
2020-11-12 15:21:11 +00:00
Michal Simek 942d0c7c1c Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms
Jolly left the company and Siva (DP) has moved to different possition
that's why it is necessary to change code ownership.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I546d9a0f7a2abd0c7a65be807725bc609160f3b2
2020-11-12 11:25:15 +01:00
Venkatesh Yadav Abbarapu e9930d42c7 plat: xilinx: Use fno-jump-tables flag in CPPFLAGS
From GCC-9 implementation of switch case was generated through jump tables,
because of which we are seeing 1MB increase in rodata section. To reduce
the size we are recommending to use fno-jump-tables.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I069733610809b8299fbf641f0ae35b359a8afd69
2020-11-12 10:40:16 +01:00
Davorin Mista a8b10c6490 zynqmp: pm: update error codes to match Linux and PMU Firmware
All EEMI error codes start with value 2000.

Note: Legacy error codes ARGS (=1) and NOTSUPPORTED (=4) returned by
current ATF code have been left in place.

Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I939afa85957cac88025d82a80f9f6dd49be993b6
2020-11-12 10:27:14 +01:00
Mirela Simonovic c23cf05303 zynqmp: pm: Filter errors related to clock gate permissions
Linux clock framework cannot properly deal with these errors. When the
error is related to the lack of permissions to control the clock we
filter the error and report the success to linux. Before recent changes
in clock framework across the stack, this was done in the PMU-FW as a
workaround. Since the PMU-FW now handles clocks and the permissions to
control them using general principles rather than workarounds, it can
no longer distinguish such exceptions and it has to return no-access
error.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I1491a80e472f44e322a542b29a20eb1cb3319802
2020-11-12 10:26:57 +01:00
Manish Pandey d01f31c036 Merge "make_helpers: tbbr: Fix FWU certificate generation" into integration 2020-11-09 15:47:34 +00:00
Manish V Badarkhe 8cdb169339 make_helpers: tbbr: Fix FWU certificate generation
Provide missed command line parameters such as KEY_ALG, HASH_ALG
and KEY_SIZE while generating the FWU certificate.

Signed-off-by: Gilad Ben Yossef <Gilad.BenYossef@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I017fa3fff844f4262ae2441cbc9fee909d357fb3
2020-11-09 08:51:10 +00:00
Alexei Fedorov 8109d2dd69 Merge "Use constant stack size with RECLAIM_INIT_CODE" into integration 2020-10-29 18:00:13 +00:00
Manish Pandey 271708e064 Merge changes from topic "mbox-patches" into integration
* changes:
  intel: common: Fix non-MISRA compliant code v2
  intel: mailbox: Fix non-MISRA compliant code
  intel: mailbox: Mailbox error recovery handling
  intel: mailbox: Enable sending large mailbox command
  intel: mailbox: Use retry count in mailbox poll
  intel: mailbox: Ensure time out duration is predictive
  intel: mailbox: Read mailbox response even there is an error
  intel: mailbox: Driver now handles larger response
  intel: common: Change how mailbox handles job id & buffer
  intel: common: Improve readability of mailbox read response
  intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
  intel: common: Remove urgent from mailbox async
  intel: common: Improve mailbox driver readability
2020-10-29 11:17:01 +00:00
David Horstmann 3ed5606bd1 Use constant stack size with RECLAIM_INIT_CODE
Currently, when RECLAIM_INIT_CODE is set, the
stacks are scaled to ensure that the entirety
of the init section can be reclaimed as stack.

This causes an issue in lib/psci/aarch64/psci_helpers.S,
where the stack size is used for cache operations in
psci_do_pwrdown_cache_maintenance(). If the stacks
are scaled, then the PSCI code may fail to invalidate
some of the stack memory before power down.

Resizing stacks is also not good for stability in general,
since code that works with a small number of cores may
overflow the stack when the number of cores is increased.

Change to make every stack be PLATFORM_STACK_SIZE big,
and allow the total stack to be smaller than the
init section.

Any pages of the init section not reclaimed as
stack will be set to read-only and execute-never,
for security.

Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8
Signed-off-by: David Horstmann <david.horstmann@arm.com>
2020-10-28 17:58:49 +00:00
André Przywara fc860630f6 Merge "aarch64/arm: Add compiler barrier to barrier instructions" into integration 2020-10-28 14:34:07 +00:00
Manish Pandey 6e97b22456 Merge changes from topic "mbox-patches" into integration
* changes:
  intel: common: Clean up mailbox and sip header
  intel: clear 'PLAT_SEC_ENTRY' in early platform setup
2020-10-28 14:07:15 +00:00
Manish Pandey 350c04f6c1 Merge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration
* changes:
  mediatek: mt8192: add timer support
  mediatek: mt8192: Add reboot function for PSCI
  mediatek: mt8192: add sys_cirq driver
  mediatek: mt8192: add GPIO driver support
2020-10-28 14:04:07 +00:00
Dehui Sun 4a128018b6 mediatek: mt8192: add timer support
add timer driver.

Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7
2020-10-28 17:21:55 +08:00
Nina Wu 0f40824729 mediatek: mt8192: Add reboot function for PSCI
Add system_reset function in psci ops

Change-Id: If85be70b8ae9d6487e02626356f0ff1e78b76de9
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
2020-10-28 17:21:55 +08:00
gtk_pangao b6cec33785 mediatek: mt8192: add sys_cirq driver
1.add sys_cirq driver
2.add gic api for cirq

Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b
Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>
2020-10-28 17:21:55 +08:00
Andre Przywara 2be491b1dc aarch64/arm: Add compiler barrier to barrier instructions
When issuing barrier instructions like DSB or DMB, we must make sure
that the compiler does not undermine out efforts to fence off
instructions. Currently the compiler is free to move the barrier
instruction around, in respect to former or later memory access
statements, which is not what we want.

Add a compiler barrier to the inline assembly statement in our
DEFINE_SYSOP_TYPE_FUNC macro, to make sure memory accesses are not
reordered by the compiler.
This is in line with Linux' definition:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/include/asm/barrier.h

Since those instructions share a definition, apart from DSB and DMB this
now also covers some TLBI instructions. Having a compiler barrier there
also is useful, although we probably have stronger barriers in place
already.

Change-Id: If6fe97b13a562643a643efc507cb4aad29daa5b6
Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-10-27 16:15:00 +00:00
Manish Pandey c03657051e Merge "plat: marvell: armada: Fix dependences for target fip" into integration 2020-10-27 14:01:11 +00:00
Abdul Halim, Muhammad Hadi Asyrafi d57318b7c9 intel: common: Fix non-MISRA compliant code v2
This patch is used to fix remaining non compliant code for Intel
SoCFPGA's mailbox and sip driver. These changes include:
- Change non-interface required uint32_t into unsigned int
- Change non-negative variable to unsigned int
- Remove obsolete variable initialization to 0

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5
2020-10-27 11:21:00 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 9e285909ae intel: mailbox: Fix non-MISRA compliant code
This patch is used to fix remaining non compliant code for Intel
SocFPGA's mailbox driver. These changes include:
- adding integer literal for unsigned constant
- fix non-boolean controlling expression
- add braces even on conditional single statement bodies

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0f8fd96a3540f35ee102fd2f2369b76fa73e39e1
2020-10-27 11:20:59 +08:00
Chee Hong Ang 997560470a intel: mailbox: Mailbox error recovery handling
Attempt to restart the mailbox if the mailbox driver not able
to write any data into the mailbox command buffer.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: Ia45291c985844dec9da82839cac701347534d32b
2020-10-27 11:20:59 +08:00
Abdul Halim, Muhammad Hadi Asyrafi d14e965c03 intel: mailbox: Enable sending large mailbox command
Allow mailbox command that is larger than mailbox command FIFO buffer
size to be sent to SDM in multiple chunks.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I683d5f1d04c4fdf57d11ecae6232b7ed3fc49e26
2020-10-27 11:20:55 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 4978bc2832 intel: mailbox: Use retry count in mailbox poll
Change the main loop inside mailbox poll function from while(1) to a
retry counter named sdm_loop. This is to limit the maximum possible
looping of the function and prevent unexpected behaviour.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I63afad958fe5f656f6333b60d5a8b4c0ada3b23d
2020-10-27 11:17:41 +08:00
Chee Hong Ang d96e7cda8a intel: mailbox: Ensure time out duration is predictive
For each count down of time out counter, wait for number of
miliseconds to ensure the time out duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b
2020-10-27 11:17:40 +08:00
Chee Hong Ang 6d9f9f5ea0 intel: mailbox: Read mailbox response even there is an error
Mailbox driver should read the response data if the response length
in the response header is non-zero even the response header indicates
error (non-zero).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640
2020-10-27 11:17:40 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 39aebd358e intel: mailbox: Driver now handles larger response
This patch factorizes mailbox read response from SDM into a function.
Also fix the logic to support reading larger than 16 words response from
SDM.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5
2020-10-27 11:17:40 +08:00
Abdul Halim, Muhammad Hadi Asyrafi aad868b4d9 intel: common: Change how mailbox handles job id & buffer
This patch modifies several basic mailbox driver features to prepare for
FCS enablement:
- Job id management for asynchronous response
- SDM command buffer full

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2
2020-10-27 11:17:34 +08:00
Olivier Deprez 00ad74c7af Merge "SPMC: adjust device region for first secure partition" into integration 2020-10-26 09:51:32 +00:00
Po Xu 054af8f233 mediatek: mt8192: add GPIO driver support
add GPIO driver

Change-Id: I67a9abef078e7a62b34dfbd366b45c03892800cd
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
2020-10-26 16:21:11 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 516f32219b intel: common: Clean up mailbox and sip header
Sort and rearrange definitions in both mailbox and sip header to
increase readability and maintainability.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856
2020-10-24 11:00:42 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 941fc5c0d2 intel: common: Improve readability of mailbox read response
Rename variables to improve readability of mailbox read response and
mailbox poll response flow.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Icd33ff1d2abb28eeead15e4eb9c7f9629f8cb402
2020-10-24 11:00:42 +08:00
Chee Hong Ang 7f56f240d3 intel: clear 'PLAT_SEC_ENTRY' in early platform setup
Ensure 'PLAT_SEC_ENTRY' is cleared during early platform
setup. This is to prevent the slave CPU cores jump to the stale
entry point after warm reset when using U-Boot SPL as first
stage boot loader.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a
2020-10-24 11:00:42 +08:00
Richard Gong 1ae7b6f6b1 intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher
pre-reserved memory size between Intel service layer and secure monitor
software so we can handle JIC file authorization.

Signed-off-by: Richard Gong <richard.gong@intel.com>
Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c
2020-10-24 11:00:42 +08:00
Abdul Halim, Muhammad Hadi Asyrafi d191eb247a intel: common: Remove urgent from mailbox async
Remove urgent argument from asynchrounous mailbox command as any urgent
command should always be synchronous

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319
2020-10-24 11:00:42 +08:00
Abdul Halim, Muhammad Hadi Asyrafi f8e6a09c64 intel: common: Improve mailbox driver readability
Use pre-defined macros for return values and common mailbox arguments

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e
2020-10-24 11:00:42 +08:00
Varun Wadekar 95fca1101e Merge "docs: marvell: update ddr3 build instructions" into integration 2020-10-24 02:30:21 +00:00
Varun Wadekar 9c28689a41 Merge changes I5ae9d08b,I5cbbd7eb,Idb389223 into integration
* changes:
  plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k
  plat: marvell: armada: Fix including plat/marvell/marvell.mk file
  plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it
2020-10-24 02:29:31 +00:00
Manish Pandey 083dbb67f9 Merge "plat/qemu_sbsa: Remove cortex_a53 and aem_generic" into integration 2020-10-22 08:49:30 +00:00
Olivier Deprez d0d63afeb4 SPMC: adjust device region for first secure partition
For the first partition, mark first 2GB as device memory excluding
the Trusted DRAM region reserved for the SPMC.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I3ff110b3facf5b6d41ac2519ff6ca5e30a0a502b
2020-10-22 00:12:00 +02:00