This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING
configuration variable and is only enabled for Tegra210 platforms, for now.
Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the flow controller instead, for
power state management. But the flow controller can route the FIQ to the GICD,
as a PPI, which can then get routed to the target CPU.
This patch adds routines to enable/disable routing the legacy FIQ used by
the watchdog timers, to the GICD.
Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.
This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.
Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
This patch updates the secure interrupt handler to mark the interrupt
as complete in case the NS world has not registered a handler.
Change-Id: Iebe952305f7db46375303699b6150611439475df
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds support to the bpmp_ipc driver to allow clients to
enable/disable clocks to hardware blocks. Currently, the API only
supports SE devices.
Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90
Signed-off-by: steven kao <skao@nvidia.com>
The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.
Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds a default implementation for the platform specific
CPU standby power handler. Tegra SoCs can override this handler
with their own implementations.
Change-Id: I91e513842f194b1e2b1defa2d833bb4d9df5f06b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Modifying smmu macros to pass base address of smmu so that it can be
used with multiple smmus.
Added macro for combining smmu backup regs that can be used for multiple
smmus.
Change-Id: I4f3bb83d66d5df14a3b91bc82f7fc26ec8e4592e
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
ARM_PLAT_MT build flag is specific to Arm platforms so should not
be classified as a common build option.
Change-Id: I79e411958846759a5b60d770e53f44bbec5febe6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Commit ed51b51f7a ("Remove build option LOAD_IMAGE_V2") intended
to remove all code related to LOAD_IMAGE_V2=0 but missed a few things.
Change-Id: I16aaf52779dd4af1e134e682731328c5f1e5d622
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sections 2.2, 2.3 and 2.4 contained example code blocks that were not
being formatted properly due to missing newlines.
Change-Id: I0dbce90c931cf69e4f47d2ccbcc8bc0e20f8fd66
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
This reverts commit 2f37046524 ("Add support for the SMC Calling
Convention 2.0").
SMCCC v2.0 is no longer required for SPM, and won't be needed in the
future. Removing it makes the SMC handling code less complicated.
The SPM implementation based on SPCI and SPRT was using it, but it has
been adapted to SMCCC v1.0.
Change-Id: I36795b91857b2b9c00437cfbfed04b3c1627f578
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the
size of translation tables by increasing the maximum permitted value
of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and
VSTCR_EL2.
This feature is supported in AArch64 state only.
This patch adds support for this feature to both versions of the
translation tables library. It also removes the static build time
checks for virtual address space size checks to runtime assertions.
Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
This patch adds more details on #include directive use, including (pun
not intended) the desired ordering, grouping and variants (<> or "").
Change-Id: Ib024ffc4d3577c63179e1bbc408f0d0462026312
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
This patch attempts to make the guidelines clearer by reordering
the sections and grouping similar topics.
Change-Id: I1418d6fc060d6403fe3e1978f32fd54b8793ad5b
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Adds a link from user-guide.rst to coding-guidelines.rst and merges
the information about using checkpatch from both files into the user
guide document.
Change-Id: Iffbb4225836a042d20024faf28b8bdd6b2c4043e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
This content has been imported and adapted from the TF GitHub wiki
article 'ARM-Trusted-Firmware-Coding-Guidelines'.
The aim is to increase the visibility of the coding guidelines by
including them as part of the documentation that is within the TF
repository.
Additionally, the documentation can then be linked to by other
documents in the docs/ directory without worrying about broken links
to, for example, the external wiki.
Change-Id: I9d8cd6b5117b707c1a113baeba7fc5e1b4bf33bc
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Commit 033648652f ("Make TF UUID RFC 4122 compliant") changed the scanf
parsing string to handle endianness correctly.
However that changed the number of items sscanf handles, without
adjusting the sanity check just below.
Increase the expected return value from 11 to 16 to let fiptool handle
UUIDs given as blob parameters correctly again.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Clean up the NOTICE() and FATAL_MSG() outputs, so that they contain
proper newlines and BL2 prefixes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Method cpld_reset_cpu of bl31 is called from the Linux kernel and uses
GPIO6, GPIO2 pins as SPI bus lines to control the CPLD device. But in the
kernel GPIO6_8 pin are initialized to work in interrupt mode instead of
the input/output mode. This leads to the fact that the SPI bus becomes
non-functional. In this patch we switch the GPIO6_8 pin back to the
input-output mode.
Signed-off-by: Sergii Boryshchenko <sergii.boryshchenko@globallogic.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
The ATF code fails to build with PMIC_ROHM_BD9571=0, add the missing
function into the PWRC code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This reverts commit d48536e2f9,
which misbehaves on R-Car H3 ES2.0. Until the reason for that
misbehavior is understood, revert the commit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Current implementation of i.MX8QX power management related
features does NOT optimize power number, all system resources
like CCI, DDR, and A cluster etc. are kept in STBY mode (powered
ON) when system suspend or CPU hotplug.
To lower the power number, OFF mode should be adopted for those
system resources whenever they can be OFF, A cluster will be OFF
if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF
if system suspend, IRQ steer can be OFF if the wakeup source is
belonged to system controller partition, so wakeup source runtime
check is used to determine if IRQ steer can be OFF before system
suspend.
If resources are powered off for suspend, they should be restored
properly after system resume.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Current implementation of i.MX8QM power management related
features does NOT optimize power number, all system resources
like CCI, DDR, and A cluster etc. are kept in STBY mode (powered
ON) when system suspend or CPU hotplug.
To lower the power number, OFF mode should be adopted for those
system resources whenever they can be OFF, A cluster will be OFF
if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF
if system suspend, IRQ steer can be OFF if the wakeup source is
belonged to system controller partition, so wakeup source runtime
check is used to determine if IRQ steer can be OFF before system
suspend.
If resources are powered off for suspend, they should be restored
properly after system resume.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
After the removal of deprecated interfaces in TF 2.0 the migration to
the new GIC driver interfaces was done incorrectly in rk3328 and rk3368:
2d6f1f01b1 ("rockchip: Migrate to new interfaces").
In the GICv2 driver it is mandated that all interrupts are Group 0
interrupts. This patch simply moves all Group 1 interrupts to Group 0.
Change-Id: I224c0135603eb5b81bd512976361500c0d129a91
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Varun Wadekar
Jeetesh Burman
steven kao
Pritesh Raithatha
Sandrine Bailleux
Ryan Grachek
Antonio Niño Díaz
Paul Beesley
Sathees Balya
Andre Przywara
Marek Vasut
Sergii Boryshchenko
Anson Huang
Florian La Roche
Joel Hutton