The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which will be reflected by
this register.
This patch reads the control register before processing
a video memory resize request. An error code, -ENOTSUP,
is returned if the feature is locked.
Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This patch removes the weakly defined per-platform SiP handler
as all platforms implement this handler, defeating the need for
a weak definition.
Change-Id: Id4c7e69163d2635de1813f5a385ac874253a8da9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e
Fake system suspend relies on software running on EL3
to trigger a warm reset.
Revert enabling fake system suspend, as the software
running on El3 is not allowed to trigger a warm reset.
Change-Id: I6035f2a7bcb0a4ad50a62c5bc5239226c625ee5e
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.
This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.
Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.
The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.
Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.
Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Macro assert(e) request 'e' is a bool type, if useing other
type, MISRA report a "The Essential Type Model" violation,
Add a judgement to fix the defects, if 'e' is not bool type.
Remove unused code [Rule 2.5]
Fix the essential type model violation [Rule 10.6, 10.7]
Use local parameter to raplace function parameter [Rule 17.8]
Change-Id: Ifce932addbb0a4b063ef6b38349d886c051d81c0
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
to be compatible with whatever operation they're used in [Rule
10.1]
* Fix implicit widening of composite assignment [Rule 10.6]
Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
to be compatible with whatever operation they're used in [Rule
10.1]
* Fix implicit widening of composite assignment [Rule 10.6]
Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Commit 4c0d039076 ("Rework type usage in Trusted Firmware") changed
the type usage in struct declarations, but did not touch the definition
side. Fix the type mismatch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions to this change in order to retain
header groupings and where there are headers within #if statements.
Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
This patch moves the GPU reset state check, during VideoMem resize, to the
common SiP handler, to reduce code duplication.
Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.
NOTE: Files that have been imported by FreeBSD have not been modified.
[0]: https://spdx.org/
Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
On Tegra systems, there are multiple software components that
require to interact with MCE. The components can either be 32-bit
or 64-bit payloads. This patch supports MCE SMC functions ID for
AARCH32 and AARCH64 architectures to support such clients.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds support for fake system suspend (SC7).
This is a debug mode, to ensure that a different code path is
executed for cases like pre-silicon development, where a
full-fledged SC7 is not possible in early stages.
This particular patch ensures that, if fake system suspend is
enabled (denoted by tegra_fake_system_suspend variable
having a non-zero value), instead of calling WFI, a request
for a warm reset is made for starting the SC7 exit procedure.
This ensures that the code path of kernel->ATF and back to
kernel is executed without depending on other components
involved in SC7 code path.
Additionally, this patch also adds support for SMC call
from kernel, enabling fake system suspend mode.
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch allows the NS world to pass 64-bit base address for
the Video Memory carveout region.
Change-Id: I7e47cc1f5425bd39c6763755b801517013e1e0cd
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.
The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.
Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch removes the restriction of allowing SiP calls only from the
non-secure world. The secure world can issue SiP calls as a result of
this patch now.
Change-Id: Idd64e893ae8e114bba0196872d3ec544cac150bf
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch implements a handler for common SiP calls. A weak
implementation for the SoC-specific handler has been provided
which can be overridden by SoCs to implement any custom SiP
calls.
Change-Id: I45122892a84ea35d7b44be0f35dc15f6bb95193e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch converts the common SiP handler to SoC specific SiP
handler. T210 and T132 have different SiP SMCs and so it makes
sense to move the SiP handler to soc/t132 and soc/t210 folders.
Change-Id: Idfe48384d63641137d74a095432df4724986b241
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch implements support for T132 (Denver CPU) based Tegra
platforms.
The following features have been added:
* SiP calls to switch T132 CPU's AARCH mode
* Complete PSCI support, including 'System Suspend'
* Platform specific MMIO settings
* Locking of CPU vector registers
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds support to reserve a memory carveout region in the
DRAM on Tegra SoCs. The memory controller provides specific registers
to specify the aperture's base and size. This aperture can also be
changed dynamically in order to re-size the memory available for
DRM video playback. In case of the new aperture not overlapping
the previous one, the previous aperture has to be cleared before
setting up the new one. This means we do not "leak" any video data
to the NS world.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Anthony Zhou
Varun Wadekar
Vignesh Radhakrishnan
Jeetesh Burman
Antonio Nino Diaz
Masahiro Yamada
Isla Mitchell
dp-arm
Harvey Hsieh
Wayne Lin