Commit Graph

806 Commits

Author SHA1 Message Date
Olivier Deprez fbe228b1c1 Merge "allwinner: Add a msgbox driver for use with SCPI" into integration 2020-02-26 09:09:22 +00:00
Mark Dykes 896d684de6 Merge changes from topic "console_t_cleanup" into integration
* changes:
  marvell: Consolidate console register calls
  uniphier: Use generic console_t data structure
  spe: Use generic console_t data structure
  LS 16550: Use generic console_t data structure
  stm32: Use generic console_t data structure
  rcar: Use generic console_t data structure
  a3700: Use generic console_t data structure
  16550: Use generic console_t data structure
  imx: Use generic console_t data structure
2020-02-25 23:39:33 +00:00
Mark Dykes c723ef018f Merge changes from topic "console_t_cleanup" into integration
* changes:
  coreboot: Use generic base address
  skeletton: Use generic console_t data structure
  cdns: Use generic console_t data structure
2020-02-25 23:38:46 +00:00
Mark Dykes 093dce7032 Merge "pl011: Use generic console_t data structure" into integration 2020-02-25 23:16:14 +00:00
Mark Dykes ad8922fcd9 Merge "meson: Use generic console_t data structure" into integration 2020-02-25 21:08:21 +00:00
Mark Dykes cfcf4e9da9 Merge "arm/css/scpi: Don't panic if the SCP fails to respond" into integration 2020-02-25 20:25:35 +00:00
Andre Przywara e21a788ee1 coreboot: Use generic base address
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location for the coreboot memory console.
This removes the base member from the coreboot specific data structure,
but keeps the struct console_cbmc_t and its size member.

Change-Id: I7f1dffd41392ba3fe5c07090aea761a42313fb5b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Andre Przywara f695e1e01a pl011: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Andre Przywara 489e298744 meson: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I07a07677153d3671ced776671e4f107824d3df16
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Andre Przywara e8ada80a84 skeletton: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I347849424782333149e5912a25cc0ab9d277a201
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Andre Przywara 78b40dce64 cdns: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I9f8b55414ab7965e431e3e86d182eabd511f32a4
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Andre Przywara c10db6deb1 stm32: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Andre Przywara c01ee06b53 rcar: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I836e26ff1771abf21fd460d0ee40e90a452e9b43
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Andre Przywara 3968bc08ab a3700: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I89c3ab2ed85ab941d8b38ced48474feb4aaa8b7e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Andre Przywara 98964f0523 16550: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Andre Przywara d7873bcd54 imx: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I058f793e4024fa7291e432f5be374a77faf16f36
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Varun Wadekar d4b29105f4 include: move MHZ_TICKS_PER_SEC to utils_def.h
This patch moves the MHZ_TICKS_PER_SEC macro to utils_def.h
for other platforms to use.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6c4dc733f548d73cfdb3515ec9ad89a9efaf4407
2020-02-20 09:25:45 -08:00
Sandrine Bailleux 522338b931 Merge changes I72846d86,I70c3d873,If675796a,I0dbf8091,Ie4f3ac83, ... into integration
* changes:
  rcar_gen3: plat: Minor coding style fix for rcar_version.h
  rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.6
  rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: board: Add new board revision for M3ULCB
  rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
  rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.5
  rcar_gen3: plat: Change fixed destination address of BL31 and BL32
2020-02-19 15:29:23 +00:00
Sandrine Bailleux 6cec570246 Merge "TBBR: Reduce size of hash buffers when possible" into integration 2020-02-19 15:17:56 +00:00
Sandrine Bailleux 564074c284 Merge "TBBR: Reduce size of ECDSA key buffers" into integration 2020-02-19 15:17:48 +00:00
Mark Dykes 76ce1028b0 Merge "coverity: fix MISRA violations" into integration 2020-02-18 19:19:00 +00:00
Zelalem 2fe75a2de0 coverity: fix MISRA violations
Fixes for the following MISRA violations:
- Missing explicit parentheses on sub-expression
- An identifier or macro name beginning with an
  underscore, shall not be declared
- Type mismatch in BL1 SMC handlers and tspd_main.c

Change-Id: I7a92abf260da95acb0846b27c2997b59b059efc4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
2020-02-18 10:47:46 -06:00
Sandrine Bailleux 0b4e59211b TBBR: Reduce size of hash buffers when possible
The TBBR implementation extracts hashes from certificates and stores
them in static buffers. TF-A supports 3 variants of SHA right now:
SHA-256, SHA-384 and SHA-512. When support for SHA-512 was added in
commit 9a3088a5f5 ("tbbr: Add build flag
HASH_ALG to let the user to select the SHA"), the hash buffers got
unconditionally increased from 51 to 83 bytes each. We can reduce that
space if we're using SHA-256 or SHA-384.

This saves some BSS space in both BL1 and BL2:
- BL1 with SHA-256: saving 168 bytes.
- BL1 with SHA-384: saving 80 bytes.
- BL2 with SHA-256: saving 384 bytes.
- BL2 with SHA-384: saving 192 bytes.

Change-Id: I0d02e5dc5f0162e82339c768609c9766cfe7e2bd
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-02-18 09:47:12 +01:00
Sandrine Bailleux 495599cd0a TBBR: Reduce size of ECDSA key buffers
The TBBR implementation extracts public keys from certificates and
stores them in static buffers. DER-encoded ECDSA keys are only 91 bytes
each but were each allocated 294 bytes instead. Reducing the size of
these buffers saves 609 bytes of BSS in BL2 (294 - 91 = 203 bytes for
each of the 3 key buffers in use).

Also add a comment claryfing that key buffers are tailored on RSA key
sizes when both ECDSA and RSA keys are used.

Change-Id: Iad332856e7af1f9814418d012fba3e1e9399f72a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-02-18 09:46:55 +01:00
Chiaki Fujii cc4e7ad49e rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.40.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: If675796a2314e769602af21bf5cc6b10962d4f29
2020-02-15 10:46:00 +01:00
Chiaki Fujii 1f420077b6 rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.39.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I0dbf8091f9de9bb6d2d4f94007a5813fff14789f
2020-02-15 10:46:00 +01:00
Yusuke Goda 0fdfe245f1 rcar_gen3: drivers: board: Add new board revision for M3ULCB
Board Revision[2:0]
 3'b000 Rev1.0
 3'b011 Rev3.0 [New]

Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: Ie4f3ac83cc20120ede21052f7452327049565e60
2020-02-15 10:46:00 +01:00
Chiaki Fujii ba63b5c93e rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.38.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I49cf8f778b849a6ee97bc9f6948c45b07dc467b1
2020-02-15 10:46:00 +01:00
Samuel Holland 50cabf6d22 allwinner: Add a msgbox driver for use with SCPI
The function names follow the naming convention used by the existing
ARM SCPI client.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I543bae7d46e206eb405dbedfcf7aeba88a12ca48
2020-02-12 21:18:21 -06:00
Samuel Holland 98367c8061 arm/css/scpi: Don't panic if the SCP fails to respond
Instead, pass back the error to the calling function. This allows
platform code to fall back to another PSCI implementation if
scpi_wait_ready() or a later SCPI command fails.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib4411e63c2512857f09ffffe1c405358dddeb4a6
2020-02-12 21:16:46 -06:00
Sandrine Bailleux c83d66ec63 Merge changes Ib68092d1,I816ea14e into integration
* changes:
  plat: marvell: armada: scp_bl2: allow loading up to 8 images
  plat: marvell: armada: add support for loading MG CM3 images
2020-02-12 15:51:42 +00:00
Sandrine Bailleux 21c4f56fa7 Merge changes from topic "lm/fconf" into integration
* changes:
  arm-io: Panic in case of io setup failure
  MISRA fix: Use boolean essential type
  fconf: Add documentation
  fconf: Move platform io policies into fconf
  fconf: Add mbedtls shared heap as property
  fconf: Add TBBR disable_authentication property
  fconf: Add dynamic config DTBs info as property
  fconf: Populate properties from dtb during bl2 setup
  fconf: Load config dtb from bl1
  fconf: initial commit
2020-02-11 16:15:45 +00:00
Mark Dykes 513b6165ee Merge "coverity: Fix MISRA null pointer violations" into integration 2020-02-10 17:20:53 +00:00
Aditya Angadi 31e703f995 drivers/arm/scmi: allow use of multiple SCMI channels
On systems that have multiple platform components that can interpret the
SCMI messages, there is a need to support multiple SCMI channels (one
each to those platform components). Extend the existing SCMI interface
that currently supports only a single SCMI channel to support multiple
SCMI channels.

Change-Id: Ice4062475b903aef3b5e5bc37df364c9778a62c5
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-02-07 19:24:17 +05:30
Aditya Angadi f893160690 drivers/mhu: derive doorbell base address
In order to allow the MHUv2 driver to be usable with multiple MHUv2
controllers, use the base address of the controller from the platform
information instead of the MHUV2_BASE_ADDR macro.

Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-02-07 19:24:17 +05:30
Louis Mayencourt ab1981db9e fconf: initial commit
Introduce the Firmware CONfiguration Framework (fconf).

The fconf is an abstraction layer for platform specific data, allowing
a "property" to be queried and a value retrieved without the requesting
entity knowing what backing store is being used to hold the data.

The default backing store used is C structure. If another backing store
has to be used, the platform integrator needs to provide a "populate()"
function to fill the corresponding C structure.
The "populate()" function must be registered to the fconf framework with
the "FCONF_REGISTER_POPULATOR()". This ensures that the function would
be called inside the "fconf_populate()" function.

A two level macro is used as getter:
- the first macro takes 3 parameters and converts it to a function
  call: FCONF_GET_PROPERTY(a,b,c) -> a__b_getter(c).
- the second level defines a__b_getter(c) to the matching C structure,
  variable, array, function, etc..

Ex: Get a Chain of trust property:
    1) FCONF_GET_PROPERY(tbbr, cot, BL2_id) -> tbbr__cot_getter(BL2_id)
    2) tbbr__cot_getter(BL2_id) -> cot_desc_ptr[BL2_id]

Change-Id: Id394001353ed295bc680c3f543af0cf8da549469
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-02-07 13:29:09 +00:00
Zelalem 466bb285c6 coverity: Fix MISRA null pointer violations
Fix code that violates the MISRA rule:
MISRA C-2012 Rule 11.9: Literal "0" shall not be used as
null pointer constant.

The fix explicitly checks whether a pointer is NULL.

Change-Id: Ibc318dc0f464982be9a34783f24ccd1d44800551
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
2020-02-05 14:53:02 -06:00
Zelalem e6937287e4 Coverity: remove unnecessary header file includes
This patch removes unnecessary header file includes
discovered by Coverity HFA option.

Change-Id: I2827c37c1c24866c87db0e206e681900545925d4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
2020-02-04 10:23:51 -06:00
Grzegorz Jaszczyk 8164605513 plat: marvell: armada: add support for loading MG CM3 images
In order to access MG SRAM, the amb bridge needs to be configured which is
done in bl2 platform init.

For MG CM3, the image is only loaded to its SRAM and the CM3 itself is
left in reset. It is because the next stage bootloader (e.g. u-boot)
will trigger action which will take it out of reset when needed. This
can happen e.g. when appropriate device-tree setup (which has enabled
802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be
running.

Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-01-30 23:13:07 +01:00
Alexei Fedorov f69a5828b7 Merge "Use correct type when reading SCR register" into integration 2020-01-30 16:55:55 +00:00
Alexei Fedorov 8c105290f3 Measured Boot: add function for hash calculation
This patch adds 'calc_hash' function using Mbed TLS library
required for Measured Boot support.

Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-01-28 16:51:40 +00:00
Louis Mayencourt f1be00da0b Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-01-28 11:10:48 +00:00
Lionel Debieve 0581a88778 spi: stm32_qspi: Add QSPI support
Add QSPI support (limited to read interface).
Implements the memory map and indirect modes.
Low level driver based on SPI-MEM operations.

Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
2020-01-20 11:32:59 +01:00
Lionel Debieve 695f7df852 fmc: stm32_fmc2_nand: Add FMC2 driver support
Add fmc2_nand driver support. The driver implements
only read interface for NAND devices.

Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
2020-01-20 11:32:59 +01:00
Lionel Debieve a13550d0ec Add SPI-NOR framework
SPI-NOR framework is based on SPI-MEM framework using
spi_mem_op execution interface.

It implements read functions and allows NOR configuration
up to quad mode.
Default management is 1 data line but it can be overridden
by platform.
It also includes specific quad mode configuration for
Spansion, Micron and Macronix memories.

Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
2020-01-20 11:32:59 +01:00
Lionel Debieve c3e5773904 Add SPI-NAND framework
This framework supports SPI-NAND and is based on the
SPI-MEM framework for SPI operations. It uses a common high
level access using the io_mtd.

It is limited to the read functionalities.

Default behavior is the basic one data line operation
but it could be overridden by platform.

Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
2020-01-20 11:32:59 +01:00
Lionel Debieve 05e6a5638b Add SPI-MEM framework
This framework supports SPI operations using a common
spi_mem_op structure:
 - command
 - addr
 - dummy
 - data

The framework manages SPI bus configuration:
 - speed
 - bus width (Up to quad mode)
 - chip select

Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
2020-01-20 11:32:59 +01:00
Lionel Debieve b114abb609 Add raw NAND framework
The raw NAND framework supports SLC NAND devices.

It introduces a new high level interface (io_mtd) that
defines operations a driver can register to the NAND framework.
This interface will fill in the io_mtd device specification:
	- device_size
        - erase_size
that could be used by the io_storage interface.

NAND core source file integrates the standard read loop that
performs NAND device read operations using a skip bad block strategy.
A platform buffer must be defined in case of unaligned
data. This buffer must fit to the maximum device page size
defined by PLATFORM_MTD_MAX_PAGE_SIZE.

The raw_nand.c source file embeds the specific NAND operations
to read data.
The read command is a raw page read without any ECC correction.
This can be overridden by a low level driver.
No generic support for write or erase command or software
ECC correction.

NAND ONFI detection is available and can be enabled using
NAND_ONFI_DETECT=1.
For non-ONFI NAND management, platform can define required
information.

Change-Id: Id80e9864456cf47f02b74938cf25d99261da8e82
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
2020-01-20 11:32:59 +01:00
Soby Mathew 45cc606ea7 Merge changes from topic "ld/mtd_framework" into integration
* changes:
  io: change seek offset to signed long long
  compiler_rt: Import aeabi_ldivmode.S file and dependencies
2020-01-17 17:41:21 +00:00
Manish Pandey 22c2316dfe Merge "console: 16550: Prepare for skipping initialisation" into integration 2020-01-14 14:09:58 +00:00